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Voogel, Martin L.; Frans, Yohan; Ouellette, Matt; Coppens, Jason; Ahmad, Saleh; Dastidar, Jaideep; Mohsen, Ehab; Dada, Faisal; Thompson, Michael O.; Wittig, Ralph; Bauer, Trevor; Singh, Gaurav

doi:10.1109/hcs49909.2020.9220682

Cited by 10 publications

(5 citation statements)

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“…Nowadays, FPGAs contain embedded memory blocks (block RAM), multipliers (DSP), and even embedded processors cores, known as System-on-Chip FPGA (SoC FPGA) [113]. In addition, current multiprocessor system-on-chip (MPSoC) systems also include real-time processors, GPUs or AI modules [114,115] on the same die. These devices are growing more and more complex; therefore, the use of high-level synthesis tools allows further abstraction using C, C++ or SystemC to transform algorithm descriptions into register-transfer level code, allowing to speed up the hardware design process on the FPGA.…”

Section: Field Programmable Gate Arrays (Fpgas) 241 Evolution Of Fpga...mentioning

confidence: 99%

Hardware Architectures for Real-Time Medical Imaging

et al. 2021

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Medical imaging is considered one of the most important advances in the history of medicine and has become an essential part of the diagnosis and treatment of patients. Earlier prediction and treatment have been driving the acquisition of higher image resolutions as well as the fusion of different modalities, raising the need for sophisticated hardware and software systems for medical image registration, storage, analysis, and processing. In this scenario and given the new clinical pipelines and the huge clinical burden of hospitals, these systems are often required to provide both highly accurate and real-time processing of large amounts of imaging data. Additionally, lowering the prices of each part of imaging equipment, as well as its development and implementation, and increasing their lifespan is crucial to minimize the cost and lead to more accessible healthcare. This paper focuses on the evolution and the application of different hardware architectures (namely, CPU, GPU, DSP, FPGA, and ASIC) in medical imaging through various specific examples and discussing different options depending on the specific application. The main purpose is to provide a general introduction to hardware acceleration techniques for medical imaging researchers and developers who need to accelerate their implementations.

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Section: Field Programmable Gate Arrays (Fpgas) 241 Evolution Of Fpga...mentioning

confidence: 99%

Hardware Architectures for Real-Time Medical Imaging

et al. 2021

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“…Tuning knobs is difficult in the presence of heterogeneous hardware. Hardware accelerators, in the form of GPUs [26], FP-GAs [36,67], TPUs [44], and vision chips [1] can result in significant performance benefits for many video and analytics operations. Selecting the right values for tuning knobs across these heterogeneous accelerators can have a huge impact in the performance and efficiency of video pipelines.…”

Section: Introductionmentioning

confidence: 99%

Llama: A Heterogeneous & Serverless Framework for Auto-Tuning Video Analytics Pipelines

Romero,

Zhao,

Yadwadkar

et al. 2021

Preprint

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The proliferation of camera-enabled devices and large video repositories has given rise to a diverse set of video analytics applications. The video pipelines for these applications are DAGs of operations that transform videos, process extracted metadata, and answer questions such as, "Is this intersection congested?" The latency and resource efficiency of pipelines can be optimized using configurable knobs for each operation such as the sampling rate, batch size, or type of hardware used. However, determining efficient configurations is challenging because (a) the configuration search space is exponentially large, and (b) the optimal configuration depends on the desired latency target and the input video contents that may exercise different paths in the DAG and produce different volumes of intermediate results. Existing video analytics and processing systems leave it to the users to manually configure operations and select hardware resources. Hence, we observe that they often execute inefficiently and fail to meet latency and cost targets.We present Llama: a heterogeneous and serverless framework for auto-tuning video pipelines. Llama optimizes the overall video pipeline latency by (a) dynamically calculating latency targets peroperation invocation, and (b) dynamically running a cost-based optimizer to determine efficient configurations that meet the target latency for each invocation. This makes the problem of auto-tuning large video pipelines tractable and allows us to handle input dependent behavior, conditional branches in the DAG, and execution variability. It also allows us to dynamically target heterogenous hardware and minimize execution cost. We describe the algorithms in Llama and evaluate it on a cloud platform using serverless CPU and GPU resources. We show that compared to state-of-the-art cluster and serverless video analytics and processing systems, Llama achieves 7.9× lower latency and 17.2× cost reduction on average.

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“…Moreover, CPU-based TEEs do not directly enable isolated execution on accelerators such as GPUs [31], FPGAs [45,88], or TPUs [53]. Slowing trends in process scaling are motivating specialized hardware engines in order to achieve scalable performance [50].…”

Section: Introductionmentioning

confidence: 99%

ShEF: Shielded Enclaves for Cloud FPGAs

Zhao,

Gao,

Kozyrakis

2021

Preprint

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FPGAs are now used in public clouds to accelerate a wide range of applications, including many that operate on sensitive data such as financial and medical records. We present ShEF, a trusted execution environment (TEE) for cloud-based reconfigurable accelerators. ShEF is independent from CPUbased TEEs and allows secure execution under a threat model where the adversary can control all software running on the CPU connected to the FPGA, has physical access to the FPGA, and can compromise the FPGA interface logic of the cloud provider. ShEF provides a secure boot and remote attestation process that relies solely on existing FPGA mechanisms for root of trust. It also includes a Shield component that provides secure access to data while the accelerator is in use. The Shield is highly customizable and extensible, allowing users to craft a bespoke security solution that fits their accelerator's memory access patterns, bandwidth, and security requirements at minimum performance and area overheads. We describe a prototype implementation of ShEF for existing cloud FPGAs and measure the performance benefits of customizable security using five accelerator designs.

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Cited by 10 publications

References 0 publications

Hardware Architectures for Real-Time Medical Imaging

Hardware Architectures for Real-Time Medical Imaging

Llama: A Heterogeneous & Serverless Framework for Auto-Tuning Video Analytics Pipelines

ShEF: Shielded Enclaves for Cloud FPGAs

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