XDebugger: An Elastic Solution to Dynamic Batch In-Circuit Debugging on FPGA

Abstract

In digital system design, Intellectual Property (IP) reuse technology reduces the complexity of System on a Chip (SoC) design, and improves its design efficiency. However it also brings some testing or verification difficulties. Aiming at the low efficiency of testing mechanism, the difficulty of real-time signal monitoring and non-reusability of modulelevel debugging platform for IP design, we propose an elastic solution to dynamic batch in-circuit emulating on Field Programmable Gate Array (FPGA) so as to optimize the testing process. Through the simulation debugging kit working in the computer side, the downloading pathway of stimulus signals and configuration data is created; through the simulation monitoring kit working in the FPGA side, the uploading pathway of simulation data and feedback signals is created; and with Universal Asynchronous Receiver/Transmitter (UART), the stimulus signals, configuration data, simulation data and feedback signals are transmitted between the computer side and the FPGA side. After testing of multiple IP instances, the results show that the method has strong universality and can improve the efficiency of IP verification.