X-Gen: a random test-case generator for systems and SoCs

Emek, R.; Jaeger, I.; Naveh, Y.; Bergman, George M.; Aloni, G.; Katz, Yoav; Farkash, Monica; Dozoretz, I.; Goldin, Alex

doi:10.1109/hldvt.2002.1224444

Cited by 49 publications

(19 citation statements)

References 4 publications

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“…Various solutions have been previously proposed to tackle the design verification problem [2,3,4,5]. Many of these solutions involve an automated test generator based on some form of pseudo random selection scheme to create test cases.…”

Section: Related Workmentioning

confidence: 99%

Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC

Cheng

Lim

Sun³

et al. 2008

4th IEEE International Symposium on Electronic Design, Test and Applications (Delta 2008)

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IntroductionDesign verification of system-on-chips (SoCs) is expensive and time consuming. It accounts for up to 70% of resources in a typical design project [1]. Designing digital signal processor (DSP) SoCs create further verification complexities given the range of applications and end products DSPs are employed within.In order to test a DSP design more effectively, consideration must be given to how the DSP will be used and their intended applications. The eventual real-life usages of a DSP determine the particular design features and functions that are needed in the DSP. It is these design functionalities and their complexities that must be verified in-depth. Therefore, any effective verification strategy must incorporate extensive testing with application functions.To demonstrate this, the software application level verification methodology (SALVEM) [7,8] is employed to test the Tsinghua University Application Specific DSP (THUASDSP2004) [9]. The SALVEM technique was successfully used on other SoC previously [7,8]. The aim of this paper is to describe the application of SALVEM on a real world DSP SoC; thus demonstrate its feasibility and usefulness for DSP testing. Furthermore, for verification of the DSP, SALVEM is enhanced by an automated test generator that uses genetic evolutionary methods to create tests. The THUASDSP2004 DSP is an ideal candidate for SALVEM. It was designed specifically for multimedia applications and contains common DSP function blocks such as high performance mathematical and fast data transfer units, along with other specialized modules. These DSP architectural features are to be tested by SALVEM to enhance the design and verification quality of the DSP SoC.The reminder of this paper is as follows. Section 2 summarizes related work in design verification. Section 3 describes the DSP SoC design. The SALVEM verification approach and test generator are outlined in sections 4 and 5 respectively. Section 6 provides experimental results before the paper is concluded. Related WorkVarious solutions have been previously proposed to tackle the design verification problem [2,3,4,5]. Many of these solutions involve an automated test generator based on some form of pseudo random selection scheme to create test cases. The advantage with this approach is that many test cases can be created quickly with minimal effort. However, testing may not be optimized or effective. Due to the inherently random nature of such tests, similar functions may be repeatedly tested or other important test functions overlooked. Ideally, the tests generated should cover as much of the previously untested and critical design functions.Furthermore, hardware DSP designs require special verification considerations. Some DSP design and modeling environments like Matlab or Simulink do not describe the true hardware design implementation that will be eventually tape-out. They focus on high level DSP algorithmic validation, but the actual hardware design is not tested directly [10]

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Section: Related Workmentioning

confidence: 99%

Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC

Cheng

Lim

Sun³

et al. 2008

4th IEEE International Symposium on Electronic Design, Test and Applications (Delta 2008)

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“…XGEN [4], [5], which is the test generator used at IBM for system verification, models interactions as the building blocks for test-SW generation. An interaction is a series of communication stages known as "acts"; each act is performed by some HW components.…”

Section: Related Work and Backgroundmentioning

confidence: 99%

Using Transfer-Resource Graph for Software-Based Verification of System-on-Chip

Lim

2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…To enable accurate control over constraint-based random test generation, a number of tools have been developed. Some of these techniques involve the use of program templates which define the structure of the desired test, along with primitives to control the randomization of the related data, such as opcodes, register operands, and memory addresses [1], [3], [8], [12], [17]. Improvements on these baseline techniques use coverage metrics to drive the generation of the test programs either through Markov models [15] (as in our solution) or with Bayesian networks [7].…”

mentioning

confidence: 99%

Microprocessor Verification via Feedback-Adjusted Markov Models

Wagner

Bertacco

Austin

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-The challenge of verifying a modern microprocessor design is an overwhelming one: Increasingly complex microarchitectures combined with heavy time-to-market pressure have forced microprocessor vendors to employ immense verification teams in the hope of finding the most critical bugs in a timely manner. Unfortunately, too often, size does not seem to matter in verification, as design schedules continue to slip and microprocessors find their way to the marketplace with design errors. In this paper, we describe a novel closed-loop simulation-based approach to hardware verification and present a tool called StressTest that uses our methods to locate hard-to-find corner-case design bugs and performance problems. StressTest is based on a Markov-model-driven random instruction generator with activity monitors. The model is generated from the user-specified template files and is used to generate the instructions sent to the design under test (DUT). In addition, the user specifies key activity nodes within the design that should be stressed and monitored throughout the simulation. The StressTest engine then uses closed-loop feedback techniques to transform the Markov model into one that effectively stresses the user-selected points of interest. In parallel, StressTest monitors the correctness of the DUT response and, if the design behaves against expectation, it reports a bug and a trace leading to it. Using two microarchitectures as example testbeds, we demonstrate that StressTest finds more bugs with less effort than open-loop random instruction test generation techniques.

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X-Gen: a random test-case generator for systems and SoCs

Cited by 49 publications

References 4 publications

Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC

Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC

Using Transfer-Resource Graph for Software-Based Verification of System-on-Chip

Microprocessor Verification via Feedback-Adjusted Markov Models

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