Abstract:This paper presents a 9.4 ~ 20.6 GHz low‐noise phase‐locked loop (PLL) in 0.13‐μm SiGe BiCMOS technology for 5G applications. To achieve the wideband and phase noise performance simultaneously, a four‐core Colpitts voltage‐controlled oscillato array with 2‐bit switched capacitors and 2‐bit‐control bias currents is used in the PLL loop. In order to optimize the programmable frequency divider accurately, the injection‐locking behavior model of the dual‐mode prescaler is quantitatively analyzed, which is proved t… Show more
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