Write-Energy Relaxation of MTJ-Based Quantized Neural-Network Hardware

Asano, K.; Natsui, Masanori; Hanyu, Takahiro

doi:10.1109/ismvl57333.2023.00013

Cited by 3 publications

(1 citation statement)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Especially, physical design refinement is very emerging task because parasitic components strongly limits write current margin and the cell size is 4 times larger that the CMOS standard FF. Another important aspect for implementing truly low-energy IoT device is to combine other technologies such as bit-error tolerant computation method, 33) From the system-level view, to implement a "virtual" NV-logic LSI on a commercial IC board is important for the functional verification. AMD-Xilinx's Zynq series 34) are good candidates.…”

Section: Discussionmentioning

confidence: 99%

Design of a spin–orbit-torque-based self-terminated nonvolatile register for a write/leakage-energy-minimized backup operation

Suzuki,

Hanyu

2024

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

A self-terminated nonvolatile (NV) register that is a key component of a energy-efficient LSI is proposed and its impact on minimizing write and leakage energies during a backup operation before a power-off mode is presented by combining spin-orbit-torque (SOT) devices with CMOS circuitry. The self-terminated NV-register can automatically cut off the write current pulse by continuously monitoring the voltage change due to the state transition of the SOT device. Moreover, the write completion signals can be utilized for a flag whether the circuit can go into the power-off mode which results in the minimization of leakage energy consumption. A case study is performed using a 45nm CMOS technology which results in 71\% of total energy reduction in the backup operation compared to that of a typical worst-case design.

show abstract

Section: Discussionmentioning

confidence: 99%