Worst-case performance analysis of parallel, communicating software processes

Siebenborn, A.; Bringmann, Oliver

doi:10.1145/774789.774798

Cited by 17 publications

(10 citation statements)

References 8 publications

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“…In the last years, a lot of work has been spent to these topics of simulating [10] and verifying SystemC based designs e.g. by performance and communication analysis methods [18], [19]. Please refer to these papers for further information.…”

Section: Related Workmentioning

confidence: 99%

Timing Simulation of Interconnected AUTOSAR Software-Components

Krausé¹,

Bringmann²,

Hergenhan³

et al. 2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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AUTOSAR is a recent specification initiative which focuses on a model-driven architecture like methodology for automotive applications. However, needed engineering steps, or how-to-come from a logical to a technical architecture respectively implementation, are not well supported by tools, yet. In contrast, SystemC offers a comprehensive way to simulate, analyze, and verify software. Furthermore, it is even able to take the timing behavior of underlying hardware and communication paths into account. Already at a first glance, there are many similarities with respect to the modeling structure between the both concepts. Therefore, this paper discusses approaches on how to use SystemC during the design process of AUTOSAR-conform systems. PV untimed structural com. CDMA CP untimed P2P communication CC cycle accurate communication CAN COMMUNICATION REFINEMENT FLOW CPT timed P2P communication timing approx. communication CAN PVT CP untimed parallel processes COMPUTATION REFINEMENT FLOW CC cycle accurate computation CAN RTOS RTOS CPU CPU CPT timed parallel processes scheduled processes approximate timing RTOS CPU Model PVT PV untimed scheduled processes RTOS PV untimed structural com. CDMA CP untimed P2P communication CC cycle accurate communication CAN COMMUNICATION REFINEMENT FLOW CPT timed P2P communication timing approx. communication CAN PVT PV untimed structural com. CDMA PV untimed structural com. CDMA untimed structural com. CDMA CDMA CP untimed P2P communication CP untimed P2P communication CC cycle accurate communication CAN CC cycle accurate communication CAN CAN COMMUNICATION REFINEMENT FLOW CPT timed P2P communication CPT timed P2P communication timing approx. communication CAN PVT timing approx. communication CAN timing approx. communication CAN CAN PVT CP

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Section: Related Workmentioning

confidence: 99%

Timing Simulation of Interconnected AUTOSAR Software-Components

Krausé¹,

Bringmann²,

Hergenhan³

et al. 2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

View full text Add to dashboard Cite

show abstract

“…In addition, it relies on a correct specified system without data loss and dead locks. In [10] an analysis technique has been presented that combines methods for WCET analysis with an approach for communication analysis for hardware synthesis [3]. This approach has been extended to consider latencies on communication channels and to determine possible conflicts on shared communication resources [11].…”

Section: Introductionmentioning

confidence: 99%

“…In this paper, we will focus on software processes. Hereby two methods that work in two different problem domains are combined: (1) static timing analysis and (2) communication analysis [10]. Static timing analysis handles code sequences with control structures, including loops with bounded iteration counts.…”

Section: Introductionmentioning

confidence: 99%

Control-Flow Aware Communication and Conflict Analysis of Parallel Processes

Siebenborn

Viehl

Bringmann

2007

2007 Asia and South Pacific Design Automation Conference

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In this paper, we present an approach for control-flow aware communication and conflict analysis of systems of parallel communicating processes. This approach allows to determine the global timing behavior of such a system and to detect communication that might produce conflicts on shared communication resources. Furthermore, we show the incorporation of temporal environment models in order to analyze their influence on the system behavior. Based on the determined conflicts, an automated allocation and binding approach for shared resources to resolve potential access conflicts is proposed. All analysis steps can be performed starting with a TLM SystemC model of the entire system without any need for user interaction. Finally, a SystemC model of a Viterbi decoder is used as case study to demonstrate the capability of our approach. I. INTRODUCTIONThe complexity of systems is steadily increasing and already today, there are designs integrating more than one processor core with different instruction sets, various interfaces, memories and specialized hardware onto a single chip. Already today, the interconnection and communication of the components is a key issue in the design of such systems. Many embedded systems are composed of different processors and communicate via shared resources. Embedded systems interact with their environment under more or less hard timing constraints. The communication in such systems has a strong influence on the global timing behavior. Methods are needed to analyze timing properties, average throughput, as well as worst case response time (WCRT). Currently, analysis of such systems is usually performed by simulation with the issue of incomplete coverage. Formal methods are needed to identify the corner cases. This paper describes new methods for formal analysis of safety-critical embedded applications with hard time constraints executed on multiple processors. These systems are usually statically scheduled and do not allow task preemption. However, a static schedule can be included as a process by our analysis methods. Unlike other approaches that operate on task graphs, our analysis approach can be applied directly on a given SystemC model as functional representation of the entire system without any user interaction.The influence of blocking communication on the timing of the system is considered by identifying synchronizing communication and by determining the time a process is stalled at such a communication. With this knowledge,

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“…By combination of the multiprocess synthesis approach presented in this paper and our communication analysis approach presented in [14], multiprocess descriptions specified in SystemC can automatically be synthesized with respect to all global timing constraints by prevention of data loss and deadlocks and by use of statically solved arbitration with deterministic timing behavior. Due to space limitations, communication analysis is out of scope of this paper, but the approach presented in [3], [14] and [15] is used. …”

mentioning

confidence: 99%

Conflict analysis in multiprocess synthesis for optimized system integration

Bringmann¹,

Siebenborn²

2005

Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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This paper presents a novel approach for multiprocess synthesis supporting well-tailored module integration at system level. The goal is to extend the local scope of existing architectural synthesis approaches in order to apply global optimization techniques across process bounds for shared system resources (e.g. memories, busses, global ALUs) during scheduling and binding. This allows an area efficient implementation of un-timed or cycle-fixed multiprocess specifications at RT or algorithmic level of abstraction. Furthermore, this approach supports environment-oriented synthesis for optimized module integration by scheduling accesses to global resources with respect to the access schedules of other modules communicating to the same global resources. As a result, dynamic access conflicts can be avoided by construction, and hence, there is no need for dynamic arbitration of bus and memory accesses with potentially unpredictable timing behavior.Up till now, several academic (Metropolis, SysXplorer) and commercial tools (CoWare ConvergenC, Summit Design Visual Elite) exist supporting modeling and analysis of SoCs. But the link to implementation has not changed substantially. Current ESL synthesis tools are focusing on supporting SystemC (Forte Design Systems Cynthesizer, Celoxica Agility Compiler), C/C++ (Mentor Graphics Catapult C, NEC Cyber) or SystemVerilog (Bluespec BSC). Furthermore, first steps towards automated refinement of transaction-level models have been done (SpiraTech Cohesive).However, today's high-level synthesis approaches are still component-centric and have no integral view on the entire system and its embedding environment. Therefore, each process of a system is synthesized separately without respect to interacting data-dependent processes or shared global resources, and scheduling of access to global resources are determined only by means of local decisions. The designer has to ensure manually that the system communicates properly via busses, shared memories and direct interconnect. Usually, this has to be done by use of arbitration and synchronization techniques to prevent data loss and deadlocks and to provide the desired communication order. The goal is, to synthesize automatically such systems with respect to global timing constraints and without need for user-defined dynamic arbitration. This paper proposes a global synthesis technique consisting of multiprocess scheduling and binding. Our approach is based on a technique to derive the temporal relationship between parallel processes. The temporal relationship can be calculated by analyzing the communication behavior of the entire system, propagating timing constraints via synchronizing communications and calculation of simultaneously reachable states of parallel processes. This information can be used to construct a concurrency graph, which is the underlying data structure for multiprocess scheduling and binding. This paper is focused on parallel state analysis, construction of the concurrency graph as well as on multi-process scheduling a...

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Worst-case performance analysis of parallel, communicating software processes

Cited by 17 publications

References 8 publications

Timing Simulation of Interconnected AUTOSAR Software-Components

Timing Simulation of Interconnected AUTOSAR Software-Components

Control-Flow Aware Communication and Conflict Analysis of Parallel Processes

Conflict analysis in multiprocess synthesis for optimized system integration

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