Workload assignment considering NBTI degradation in multicore systems

Abstract

With continuously shrinking technology, reliability issues such as Negative Bias Temperature Instability (NBTI) has resulted in considerable degradation of device performance, and eventually the short mean-time-to-failure (MTTF) of the whole multicore system. This article proposes a new workload balancing scheme based on device-level fractional NBTI model to balance the workload among active cores while relaxing stressed ones. Starting with NBTI-induced threshold voltage degradation, we define a concept of Capacity Rate (CR) as an indication of one core's ability to accept workload. Capacity rate captures core's performance variability in terms of delay and power metrics under the impact of NBTI aging. The proposed workload balancing framework employs the capacity rates as workload constraints, applies a Dynamic Zoning (DZ) algorithm to group cores into zones to process task flows, and then uses Dynamic Task Scheduling (DTS) to allocate tasks in each zone with balanced workload and minimum communication cost. Experimental results on a 64-core system show that by allowing a small part of the cores to relax over a short time period, the proposed methodology improves multicore system yield (percentage of core failures) by 20%, while extending MTTF by 30% with insignificant degradation in performance (less than 3%).

On-Chip Dynamic Resource Management

“…This model considers not only the effects of temperature variations but also the transition between stress and recovery phases of the critical logical nets. Thus, a last class of works (Sun et al, 2014;Karpuzcu et al, 2009) is specialized on NBTI. Finally, it is worth mention that the vast majority of works consider aging mechanisms in CMOS technology.…”

“…• Dataflow applications, that are generally considered in the NoC-based many-core platform and are modeled as a task graph (e.g. Sun et al (2014); Haghbayan et al 2017).…”

“…Moreover, an interesting aspect of this work is the fact that, as by Bolchini et al (2016) sequences of subsequent core failures until the overall system denial of service are considered in the evaluation of the approach. Some other technique by Sun et al (2014) considers the mapping of application task-graphs onto many-core architectures focusing on the NBTI degradation effects. In particular the approach defines a zoning strategy to select the younger area of the resource grid to deploy the arrived applications.…”

Trends in On-chip Dynamic Resource Management

“…Recently, heterogeneous architectures [80] [81] [82], integrating asymmetric processors, GPUs or custom accelerators, have been also addressed in lifetime management. Depending on the specific architecture, the resource management approaches act on application mapping (as in the case of many-cores architectures [78] [83]), scheduling (as in the case of sharedmemory systems [74]), and/or on power-related knobs (DVFS and per-core power gating [72] [74] [75]). Another relevant aspect is that lifetime is only one of considered parameters, thus leading in most of the approaches to a co-optimization with performance or power/energy-consumption.…”

Performance/Reliability-Aware Resource Management for Many-Cores in Dark Silicon Era

“…Another mapping approach has been presented in [19]; the mapping algorithm is quite limited since it performs an almost-exhaustive exploration of the solution space and, moreover, it does not consider performance optimization in the mapping, and an enhancement in this direction seems to be infeasible. A dynamic mapping approach based on a many-core partitioning is introduced in [32]; even though the idea is interesting, it presents some limitations as it does not take into account power constraints.…”