Work in Progress: Identifying Unexpected Inter-core Interference Induced by Shared Cache

Hoornaert, Denis; Roozkhosh, Shahin; Mancuso, Renato; Caccamo, Marco

doi:10.1109/rtas52030.2021.00066

Cited by 2 publications

(2 citation statements)

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“…Even though the underlying PLIM approach [58] provides fine-grained observability and management of memory traffic between processors and memory hierarchy, it forces transactions to cross through a lower-frequency domain, i.e., that of the PL (100 MHz in our case). Because of this, an additional latency is added to each transaction due to the clock domain crossing (CDC) overhead [33,34,58]. This means that under PLIM, the latency of individual memory transactions can be significantly worse than what observed with direct memory accesses.…”

Section: Resultsmentioning

confidence: 99%

“…The same authors have also shown that the same type of module can be integrated in a wider framework in order to address the problem of memory traffic scheduling [33]. Interestingly, PLIM modules have also been used to highlight the possibility of memory-based on-chip denial-of-service attacks from remote cores under special conditions [34].…”

Section: Programmable Logic In the Middlementioning

confidence: 99%

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Relational Memory: Native In-Memory Accesses on Rows and Columns

Roozkhosh¹,

Hoornaert²,

Mun³

et al. 2021

Preprint

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Analytical database systems are typically designed to use a columnfirst data layout that maps better to analytical queries of access patterns. This choice is premised on the assumption that storing data in a row-first format leads to accessing unwanted fields; moreover, transforming rows to columns at runtime is expensive. On the other hand, new data items are constantly ingested in row-first form and transformed in the background to columns to facilitate future analytical queries. How will this design change if we can always access only the desired set of columns?In this paper, to address this question, we present a radically new approach to data transformation from rows to columns. We build upon recent advancements in commercial embedded platforms with tightly-coupled re-programmable logic to design native in-memory access on rows and columns.We propose a new database management system (DBMS) architecture that is the first hardware/software co-design. It relies on an FPGA-based accelerator to transparently transform base data to any group of columns with minimal overhead at runtime. This design allows the DBMS to access any group of columns as if it already exists in memory. Our method, termed relational memory, currently implements projection, and offers the groundwork for implementing selection, group by, aggregation, and supporting joins in hardware, thus, vastly simplifying the software logic and accelerating the query execution.We present a detailed analysis of relational memory using both synthetic benchmarks and realistic workloads. Our relational memory implementation can convert on the fly rows to arbitrary groups of columns without any latency penalty. Essentially, relational memory can load in cache the desired columns from a row-oriented base data layout as fast as reading from column-oriented base data layout by outsourcing data transformation to the hardware.

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Section: Resultsmentioning

confidence: 99%

Section: Programmable Logic In the Middlementioning

confidence: 99%