Word-interleaved cache

Kalyan, T. Venkata; Mutyam, Madhu

doi:10.1145/1393921.1393991

Cited by 6 publications

(1 citation statement)

References 33 publications

(35 reference statements)

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“…A range of parameters, including area, throughput, latency, and power consumption, can measure the SoC's performance, which directly impacts the system's performance [8,9]. The modified Fat-Tree topology proposed in this paper reduces memory requirements in intermediate nodes, thus lowering power consumption [10,11].…”

Section: Introductionmentioning

confidence: 99%

An Energy-Efficient Routing Protocol for a Modified Fat-Tree Topology in System-on-Chip Design

Yadav,

Ahmed,

Ambudkar

et al. 2023

MMEP

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The rapid evolution of integration technology has significantly influenced System-on-Chip (SoC) design, characterized by the unprecedented integration of numerous functional modules onto ever-shrinking chips. Consequently, facilitating robust communication between these burgeoning modules has become critical to optimizing system functionality and performance. Traditional Bus architecture, however, proves inadequate in realizing this goal. To circumvent these communication impediments, mesh and torus interconnected architectures have been proposed, with cores interconnected within a single chip using diverse routing strategies for seamless operation. This study investigates a deterministic, deadlock-free routing protocol for a modified Fat-Tree topology that incorporates a core module at the intermediate level.Utilizing the Sniper simulator environment for evaluation, it is demonstrated that the proposed protocol surpasses the X-Y routing method used in both mesh and torus topologies in terms of power efficiency and throughput. The results show a 4%-8% reduction in power consumption compared to other approaches, indicating the superior efficacy of the proposed method.

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Section: Introductionmentioning

confidence: 99%

An Energy-Efficient Routing Protocol for a Modified Fat-Tree Topology in System-on-Chip Design

Yadav,

Ahmed,

Ambudkar

et al. 2023

MMEP

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SFFMap: Set-First Fill mapping for an energy efficient pipelined data cache

Majumder

Mutyam

2014

2014 IEEE 32nd International Conference on Computer Design (ICCD)

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Conventionally, consecutively addressed blocks are mapped onto different sets in cache. In this work, we propose a new block address mapping, Set-First Fill (SFFMap), for pipelined L1 data caches wherein consecutively addressed data blocks are mapped onto the same set. This increases the inter-block spatial locality within the cache set. In order to exploit SFFMap, we propose to store and if possible, access the most recently used set in the cache's pipeline registers. Further, selective access (SSA) and selective update (SSU) techniques are proposed for setbuffer to increase the effectiveness of SFFMap. Our experimental evaluation for in-order and out-of-order processors with an 8-way set-associative data cache shows that SFFMap, together with SSA and SSU, achieves around 27% reduction in dynamic energy and 4-5% performance improvement. The proposed techniques need minor modifications to the existing hardware, making it an adoptable design.

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