Wire level encapsulation framework for increasing FPGA design productivity

Abstract

This thesis explores the performance impact of optimising the components of a Field Programmable Gate Array (FPGA) system down to the lowest level independently from other parts of the system. The motivation for this is that not only is the design and verification effort put in to a component reused, the optimisation effort expended in mapping, placement and routing is also reused. FPGA technology has its roots in digital circuit design and, like every silicon technology, it advances every 18 months, doubling the gate capacity available to the designer. The single largest threat to this growth is the gap that is forming between the number of available gates and the ability of designers to use these gates in the time frame of a typical design cycle. The design gap is more acutely felt in the FPGA computing community since the main perceived strength of FPGA technology is its reconfigurability. As an example, High Performance Computing (HPC) on FPGA offers a clear advantage. However, designer productivity issues are a major threat to its wide spread use. HPC is achieved on FPGA by specialising the architecture. Specialisation implies a design process. Thus, designer productivity is the main restricting factor to increasing the computing functionality that FPGA systems can offer. Reuse is recognised as a powerful approach to improving designer productivity. In the field of software design, reuse of third party software code is possible with both the static linking of pre-compiled libraries, and the dynamic linking of libraries during run-time. Even in the realms of Application Specific Integrated Circuit (ASIC) design, pre-placed and routed "hard" macros are available from third parties. However, currently implemented third party reuse schemes for FPGA design operate at either the source code or the net-list level. The full spectrum of compromises between flexibility and compositional effort have not been explored in previous works. Pre-routed FPGA components represent a reuse strategy that presents very low system composition effort at the cost of very little component flexibility. It is relatively simple to constrain component resource to regions on the surface of an FPGA device. The greater challenge lies in applying constraints on the interconnect usage of each component without adversely affecting system performance. There has been little work done to investigate the proposition of the third party reuse of pre-routed FPGA components. In order to investigate the feasibility of pre-routed FPGA components, a detailed structural model generator for FPGA architectures has been developed along with a complimentary set of design automation tools. The elements of an FPGA architecture and automated tool behaviour affected by component encapsulation are identified. This leads to a design methodology, including modified tools, facilitating the automated mapping of components to an encapsulated region of FPGA resource and interconnect without interference from any other mapped region. The methodology supports automated con...