Wide Voltage Power Device implementation in O.25μm SOI BiC-DMOS

Nitta, T.; Yanagi, S.; Miyajima, Tsukasa; Furuya, K.; Otsu, Y.; Onoda, Hiroshi; Hatasako, K.

doi:10.1109/ispsd.2006.1666141

Cited by 36 publications

(27 citation statements)

References 3 publications

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“…Therefore, we should use it properly. Figure 10 shows a HVNMOS structure in SOI technology, in which devices can be realized from 40 V to 200 V [8]. Figure 11 shows the electric equipotential line for a 160 V diode.…”

Section: Features Of Soi Device Technologymentioning

confidence: 99%

Past and Future Technology for Mixed Signal LSI

Hatasako

Nitta

Hane

et al. 2014

IEICE Trans. Electron.

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SUMMARYThis paper discusses Mixed Signal LSI technology with embedded power transistors. Trends in Mixed Signal LSI technology are explained at first. Mixed signal LSI technology has proceeded with the help of fine fabrication technology and SOI technology. The BEOL transistor is a new development, which uses InGaZnO (IGZO) as its TFT channel material. The BEOL transistor is one future device which enables 3D IC and chip shrinking technology.

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Section: Features Of Soi Device Technologymentioning

confidence: 99%

Past and Future Technology for Mixed Signal LSI

Hatasako

Nitta

Hane

et al. 2014

IEICE Trans. Electron.

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“…Due to the more active parasitic npn structure embedded in a p type LIGBT, it is theoretically possible to get a pair of equal-sized n type and p type LIGBTs if the device is excellently optimized. In the paper published in 2006 [80], a p type field LIGBT as shown in Fig. 18 was discussed.…”

Section: Dummy Metal Short (Dms) With Emitter Ballast Design In P-typmentioning

confidence: 99%

A Review of techniques used in Lateral Insulated Gate Bipolar Transistor (LIGBT)

Tee¹

2012

IOSRJEEE

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“…Such Smart Power ICs enable integration of high voltage (HV) devices for operation at greater than 5 V as well as low voltage logic and analog circuits on the same chip. BCD technologies use buried layers (Moscatelli et al, 2000) or alternatively DTI (Deep Trench Isolation) and SOI (SOI-BCD) (Nitta et al, 2006) to isolate high voltage devices. In this way high voltages (up to $100 V) and high currents (up to $10 A) can be provided in combination with low voltage logic and analog circuits.…”

Section: Smart Power Ic Technology Optionsmentioning

confidence: 99%

“…As a typical representative of a leading 0.35 mm BCD technology we have selected ''BCD6'' reported by (Moscatelli et al, 2000). As a typical example for a leading 0.35=0.25 mm BCD-SOI process we have selected the technology reported by (Nitta et al, 2006). Additionally, we have made process complexity estimates to enable relative die cost comparisons as shown in Fig.…”

Section: Figure Of Merit and Benchmarkingmentioning

confidence: 99%

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Scalable High Voltage CMOS technology for Smart Power and sensor applications

Schrems

Knaipp

Enichlmair

et al. 2008

Elektrotech. Inftech.

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Integration of low voltage analog and logic circuits as well as high-voltage (HV) devices for operation at greater than 5 V enables Smart Power ICs used in almost any system that contains electronics.HVCMOS (High-Voltage CMOS) technologies offer much lower process cost, if compared to BCD technologies, they enable multiple HV levels on a single chip, and need less effort when scaling to smaller CMOS technology nodes or when integrating embedded nonvolatile memory.In this work we propose a new 0.35 mm HVCMOS technology that can overcome the previous limitations in drive currents. It can match the low HV chip sizes (Rdson) of typical BCD processes while maintaining the low process complexity with only 2 mask level adders on top of CMOS. We also introduce a figure of merit (FOM) for comparing HV technologies. Key elements of making this newly proposed 0.35 mm HVCMOS so competitive to BCD technologies are discussed and a device lifetime of more than 10 years, operating temperatures of 150 C and ESD robustness of 4 kV HBM and higher, as well as the integration of a highly robust embedded EEPROM=Flash technology is shown.We also provide first verification results of the scalability of the proposed 0.35 mm HVCMOS technology to 0.18 mm and beyond as well as to currents of up to 8 A.Skalierbare Hochvolt-CMOS-Technologie fü r ,,Smart Power''-und Sensoranwendungen. Die Integration von analogen und digitalen Funktionen bei immer niedrigeren Versorgungsspannungen sowie deren Kombination mitHochvolt-Bauelementen mit Betriebsspannungen von deutlich mehr als 5 V sowie hoher Strombelastbarkeit ermö glicht den Aufbau von ,,Smart Power-Schaltkreisen'', die in modernen elektronischen Systemen nicht mehr wegzudenken sind. HVCMOS(Hochvolt-CMOS)-Technologien ermö glichen bei -im Vergleich zu BCD-Technologien -wesentlich geringeren Herstellungskosten verschiedene HVSpannungsebenen auf einem Chip, sie zeichnen sich auch durch leichte Skalierbarkeit aus, weiters kö nnen nichtflü chtige Speicher einfach integriert werden.In dieser Arbeit wird eine neue 0,35-m-HVCMOS-Technologie vorgestellt, die die bisherigen Grenzen bei der Stromergiebigkeit ü berwindet. Es sind mit BCD vergleichbare Chip-Grö ßen und Rdson-Werte mö glich, dennoch werden nur zwei zusä tzliche Masken benö tigt. Es werden eine Leistungskennzahl fü r den Vergleich solcher Prozesse vorgestellt und die wesentlichen Erfolgsfaktoren dieser Entwicklung diskutiert. Wesentliche Wettbewerbsfaktoren sind dabei eine Lebensdauer von > zehn Jahren, Betriebstemperaturen von 150 C und eine ESD-Festigkeit von >4 kV HBM sowie die Integration eines robusten EEPROM=Flash-Speichers. Es werden auch erste Ergebnisse der Skalierung der Bauelemente nach 0,18 m und kleiner sowie Resultate fü r die Steuerung von Strö men bis zu 8 A dargestellt.

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Wide Voltage Power Device implementation in O.25μm SOI BiC-DMOS

Cited by 36 publications

References 3 publications

Past and Future Technology for Mixed Signal LSI

Past and Future Technology for Mixed Signal LSI

A Review of techniques used in Lateral Insulated Gate Bipolar Transistor (LIGBT)

Scalable High Voltage CMOS technology for Smart Power and sensor applications

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