Wide range control of the sustaining voltage of ESD protection elements realized in a smart power technology

Gossner, Harald; Müller-Lynch, T.; Esmark, K.; Stecher, M.

doi:10.1109/eosesd.1999.818985

Cited by 19 publications

(8 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…HV bipolar devices have been extensively studied in literature [23][24][25][26][27][28][29]. The main reason resides in the ability to exactly tailor triggering and holding voltages, while featuring excellent failure currents (>5 mA/lm).…”

Section: Hv Bipolars Esd Design Challengesmentioning

confidence: 99%

ESD design challenges in state-of-the-art analog technologies

Boselli

2012

Microelectronics Reliability

View full text Add to dashboard Cite

Section: Hv Bipolars Esd Design Challengesmentioning

confidence: 99%

ESD design challenges in state-of-the-art analog technologies

Boselli

2012

Microelectronics Reliability

View full text Add to dashboard Cite

“…Protection against electrostatic discharge (ESD) in smart power technology devices has to take into account multiple bias source requirements [1][2][3][4][5][6]. Consequently devices with different blocking capability, breakdown and snapback voltages must be produced by simple layout variations [3].…”

Section: Introductionmentioning

confidence: 99%

“…Consequently devices with different blocking capability, breakdown and snapback voltages must be produced by simple layout variations [3]. To optimize the design, physical failure analysis methods are usually used to get information on position of dominant hot spots causing the damage.…”

Section: Introductionmentioning

confidence: 99%

Laser interferometric mapping of smart power ESD protection devices with different blocking capabilities

Bychikhin

Litzenberger

Kamvar

et al. 2001

31st European Solid-State Device Research Conference

Self Cite

View full text Add to dashboard Cite

We study thermal and free carrier distribution during electrostatic discharge (ESD) stress in npnp and anti-serial npn transistor ESD protection devices with different blocking capability. The thermal energy and free carrier distribution is studied using the measurements of temperature-and free carrier-induced optical phase shift. The dominant heat source in the npnp (anti-serial npn) device is due to a lateral (vertical) current flow. This is due to a different layout of the devices which also explains their different ruggedness.

show abstract

“…PAD In the case of fast switching outputs, whereby the speed of the output signal is comparable to the ESD pulse rise time, a problem exists to implement a robust local clamp approach ARRAY ( Fig. 1) [2][3][4]. Due to the constrains of multiple voltage domains; high voltage output; excessive IC area consumption LOCAL a conventional rail based ESD protection approach, based HV ESD upon active clamps, is not always cost effective.…”

Section: Introductionmentioning

confidence: 97%

A new Principle for a Self-Protecting Power Transistor Array Design

Ващенко

Hopper

2006 IEEE International Symposium on Power Semiconductor Devices &Amp; IC's

View full text Add to dashboard Cite

A new device level ESD protection solution for highform of embedded additional local regions that transform voltage NLDMOS power arrays is proposed and experimentally small parts of the array into SCR devices; (ii) during an ESD evaluated. Contrary to a conventional local clamp approach this event, applied to the array circuit, the current should flow in new concept provides a self-protection capability within the array the ESD sustainable local area of the array; (iii) during the itself. The self-protecting capability of the NLDMOS array is normal operation regime the local region with ESD protection achieved by embedding within some of the array fingers, a series . . . of distributed diffusion regions that form an additional parasitic capablities must contribute towards the useful array current. SCR structure with reversible snapback capabilities.POWER

show abstract

Wide range control of the sustaining voltage of ESD protection elements realized in a smart power technology

Cited by 19 publications

References 6 publications

ESD design challenges in state-of-the-art analog technologies

ESD design challenges in state-of-the-art analog technologies

Laser interferometric mapping of smart power ESD protection devices with different blocking capabilities

A new Principle for a Self-Protecting Power Transistor Array Design

Contact Info

Product

Resources

About