White noise in MOS transistors and resistors

Sarpeshkar, Rahul; Delbrück, Tobias; Mead, C. A.

doi:10.1109/101.261888

Cited by 241 publications

(148 citation statements)

References 8 publications

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“…Analog computation promises extreme energy-efficiency by operating close to the shot-noise limit [1]. By exploiting physical laws (e.g., conservation of charge for summation), a handful of analog devices is sufficient to perform computation.…”

Section: Abstract: Neuromorphic Chips Silicon Neurons Probabilisitimentioning

confidence: 99%

Silicon Neurons That Compute

Choudhary

Sloan

Fok

et al. 2012

Lecture Notes in Computer Science

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Abstract. We use neuromorphic chips to perform arbitrary mathematical computations for the first time. Static and dynamic computations are realized with heterogeneous spiking silicon neurons by programming their weighted connections. Using 4K neurons with 16M feed-forward or recurrent synaptic connections, formed by 256K local arbors, we communicate a scalar stimulus, quadratically transform its value, and compute its time integral. Our approach provides a promising alternative for extremely power-constrained embedded controllers, such as fully implantable neuroprosthetic decoders. Keywords: Neuromorphic chips, Silicon neurons, Probabilisitic synapses 1 Brain-Inspired Analog-Digital SystemsAnalog computation promises extreme energy-efficiency by operating close to the shot-noise limit [1]. By exploiting physical laws (e.g., conservation of charge for summation), a handful of analog devices is sufficient to perform computation. In contrast, digital computation relies on abstractions that require many more devices to achieve the same function (e.g., hundreds of transistors to add two 8-bit numbers). Furthermore, these abstractions break when noise exceeds a critical level, requiring enormous noise margins to avoid catastrophic failures. In contrast, analog degrades gracefully, allowing for operation at low noise margins, thereby saving power.However, robust and programmable computation using noisy analog circuits is challenging. Robust computation requires a distributed approach, but this is difficult because analog communication is susceptible to heterogeneity and noise. Programmable computation requires flexibility, but this is also difficult because analog computation exploits the underlying devices' fixed physical properties.In this paper, we realize robust and programmable mathematical computations with noisy and heterogeneous components using a framework inspired by the brain [2]. The brain uses graded dendritic potentials (cf. analog computation), all-or-none axonal spikes (cf. digital communication) and probabilistic synapses (cf. weighted connections). Our analog computational units are spiking silicon neurons [5]; our digital communication fabric is a packet-switched

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Section: Abstract: Neuromorphic Chips Silicon Neurons Probabilisitimentioning

confidence: 99%

Silicon Neurons That Compute

Choudhary

Sloan

Fok

et al. 2012

Lecture Notes in Computer Science

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“…Neurobiological systems seem to adapt around its mismatches to create precision in its analog computational structures [43]. With programmable systems, resolution is limited by thermal noise [60] and not in component mismatch, resulting in a lower cost for similar precision.…”

Section: Digital Strength: Lower Cost Numerical Precisionmentioning

confidence: 99%

“…As one adds another bit, one increases the apparent precision of that value by a factor of two; doubling a register size significantly increases its precision (e.g., eight bits at 0.4% to 16 bits at 0.0015%). To increase analog precision by one bit requires an increased cost of least a factor of two classically, primarily to deal with component mismatch, as well as current noise [60]. Analog precision cost is a polynomial function of the target SNR.…”

Section: Digital Strength: Lower Cost Numerical Precisionmentioning

confidence: 99%

Starting Framework for Analog Numerical Analysis for Energy-Efficient Computing

Hasler

2017

JLPEA

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Abstract:The focus of this work is to develop a starting framework for analog numerical analysis and related algorithm questions. Digital computation is enabled by a framework developed over the last 80 years. Having an analog framework enables wider capability while giving the designer tools to make reasonable choices. Analog numerical analysis concerns computation on physical structures utilizing the real-valued representations of that physical system. This work starts the conversation of analog numerical analysis, including exploring the relevancy and need for this framework. A complexity framework based on computational strengths and weaknesses builds from addressing analog and digital numerical precision, as well as addresses analog and digital error propagation due to computation. The complimentary analog and digital computational techniques enable wider computational capabilities.

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“…4a has similar noise sources associated with each corresponding transistor. These sources represent the thermal current noise per unit bandwidth of a subthreshold MOS transistor, the variance of which is given by [20], [21], (7) where the transconductance g m = κI D /U T and κ is the reciprocal subthreshold slope factor. The right half of our amplifier is similar to that of a regular folded cascode amplifier, resulting in the same effect by each corresponding transistor on the output node.…”

Section: Noise Analysismentioning

confidence: 99%

Design of a CMOS Potentiostat Circuit for Electrochemical Detector Arrays

Ayers

Gillis

Lindau

et al. 2007

IEEE Trans. Circuits Syst. I

101

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High-throughput electrode arrays are required for advancing devices for testing the effect of drugs on cellular function. In this paper, we present design criteria for a potentiostat circuit that is capable of measuring transient amperometric oxidation currents at the surface of an electrode with submillisecond time resolution and picoampere current resolution. The potentiostat is a regulated cascode stage in which a high-gain amplifier maintains the electrode voltage through a negative feedback loop. The potentiostat uses a new shared amplifier structure in which all of the amplifiers in a given row of detectors share a common half circuit permitting us to use fewer transistors per detector. We also present measurements from a test chip that was fabricated in a 0.5-μm, 5-V CMOS process through MOSIS. Each detector occupied a layout area of 35μm × 15μm and contained eight transistors and a 50-fF integrating capacitor. The rms current noise at 2kHz bandwidth is ≈ 110fA. The maximum charge storage capacity at 2kHz is 1.26 × 10 6 electrons.

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White noise in MOS transistors and resistors

Cited by 241 publications

References 8 publications

Silicon Neurons That Compute

Silicon Neurons That Compute

Starting Framework for Analog Numerical Analysis for Energy-Efficient Computing

Design of a CMOS Potentiostat Circuit for Electrochemical Detector Arrays

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