Proceedings of the Great Lakes Symposium on VLSI 2017 2017
DOI: 10.1145/3060403.3060492
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Cited by 80 publications
(11 citation statements)
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“…Random LL [111] XOR-based key insertion at random locations Yes SARlock [205] Flipping circuits to corrupt input pattern Yes Anti-SAT [206] Additional anti-SAT combinational blocks Yes TT-Lock [207] Wrong key enabling by flipping output patterns Yes NML [117] Nonvolatility of magnetic logic No Memristive array-based [116] Ta/HfO 2 memristive array with a key destruction scheme No BP-based FET [118] Tunable polarity and reconfigurability of device No MoS 2 -based FET [26] Electrical programming of individual device No and reliability of electronics systems deployed in critical applications such as electronic warfare and military aircraft. [138] While several different types of counterfeits such as cloned, recycled, overproduced, remarked, etc., exist, reports indicate that recycled ICs constitute the majority (≈80%) of all counterfeit ICs.…”
Section: Table 5 Comparison Of Different Ll Techniquesmentioning
confidence: 99%
“…Random LL [111] XOR-based key insertion at random locations Yes SARlock [205] Flipping circuits to corrupt input pattern Yes Anti-SAT [206] Additional anti-SAT combinational blocks Yes TT-Lock [207] Wrong key enabling by flipping output patterns Yes NML [117] Nonvolatility of magnetic logic No Memristive array-based [116] Ta/HfO 2 memristive array with a key destruction scheme No BP-based FET [118] Tunable polarity and reconfigurability of device No MoS 2 -based FET [26] Electrical programming of individual device No and reliability of electronics systems deployed in critical applications such as electronic warfare and military aircraft. [138] While several different types of counterfeits such as cloned, recycled, overproduced, remarked, etc., exist, reports indicate that recycled ICs constitute the majority (≈80%) of all counterfeit ICs.…”
Section: Table 5 Comparison Of Different Ll Techniquesmentioning
confidence: 99%
“…Tenacious and traceless logic locking (TTL) [13] inverts the output of a logic cone for one protected input pattern by modifying the cone via logic gate insertions or replacements. Modified logic cones now have inverted outputs only for the protected input pattern.…”
Section: Principles Of Tenacious and Traceless Logic Lockingmentioning
confidence: 99%
“…However, those two algorithms both have low corruptibility and are broken by removal attacks [11,12]. Tenacious and traceless logic locking (TTL) [13] and its enhancement, stripped functionality logic locking-Hamming distance (SFLL-HD) [14], are resilient to both SAT and removal attacks and SFLL-HD provides a solid level of corruptibility. Along with these algorithms, which lock a design on a gate-level, some algorithms lock a design on the RTL level such as SFLL-HLS [15] and ASSURE [16].…”
Section: Introductionmentioning
confidence: 99%
“…These resistant locking techniques generally fall into two categories based on how they resist the miter-based SAT attack. The first group [24,25,28,29] focuses on reducing the number of keys ruled out per attack iteration, significantly increasing the expected number of iterations. In practice however, these techniques are susceptible to removal attacks since the circuitry is typically traceable through properties such as signal probability or Boolean sensitivity [22,26].…”
Section: Introductionmentioning
confidence: 99%