WDBT: Wear Characterization, Reduction, and Leveling of DBT Systems for Non-Volatile Memory

Wu, Jin; Dong, Jian; Fang, Ruili; Zhang, Wen; Wang, Wenwen; Zuo, Decheng

doi:10.1145/3488423.3519337

Cited by 1 publication

(2 citation statements)

References 32 publications

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“…DBT optimizations have been studied widely in the literature [8,27,[38][39][40][41]. Cota et al [8] enhanced FP emulation performance by surrounding the use of the host FP unit with a minimal amount of non-FP code and deferring corner cases to the slower soft-float code.…”

Section: Related Workmentioning

confidence: 99%

“…Wu et al [38] focused on reducing the majority of writes introduced by DBT, introduced a flag to indicate where the latest value of an emulated guest register is placed, and mapped the guest register to host general-purpose registers directly. Wu et al [42] bridged the utilization gap and unleashed the full potential of host SIMD resources and emulated the guest general-purpose registers with host SIMD registers to reduce the memory access.…”

Section: Related Workmentioning

confidence: 99%

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Performance Improvements via Peephole Optimization in Dynamic Binary Translation

Xie,

Luo,

Tian

et al. 2024

Electronics

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The emergence of new instruction set architectures (ISAs) poses challenges in ensuring compatibility with legacy applications. Dynamic binary translation (DBT) serves as a crucial approach for achieving cross-ISA compatibility, enabling legacy applications to run compatibly with cross-ISAs. However, software-based translation encounters significant performance overhead, including substantial memory access and insufficient exploitation of target architecture features. The significant performance overhead challenges hinder the practical implementation of DBT. In this paper, we investigate a novel peephole optimization approach. First, we perform peephole analysis to identify redundant memory access and suboptimal instruction sequences. Next, we leverage live variable analysis to eliminate redundant memory-access instructions. Additionally, we bridge the gaps between cross-ISAs by exploiting ISA-specific features through instruction fusion. Finally, we implement the proposed optimization design using the open-source QEMU and extensively evaluate it on both ARM64 and SW64 platforms. The experimental results reveal that SPEC2006 benchmark effectively gets a maximum performance speedup of 1.52×, alongside a reduction in code size of up to 13.98%. These results affirm the effectiveness of our optimization approach in DBT performance and code sizes.

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