Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors

Abstract

This paper proposes a novel cache architecture -Way Halted Prediction -to reduce energy consumption and effective access time of set associative caches. This is achieved with the help of halt tag array and prediction circuit. Experimental evaluation of various SPEC benchmark programs on CACTI 5.3 and CASIM simulators reveal that the proposed architecture offers 33%, 6% and 3% savings in dynamic energy consumption and 1.80%, 6.13% and -1.95% saving in effective access time over conventional, way predicting and way halting cache architectures respectively.

Architectural Techniques for Improving the Power Consumption of NoC-Based CMPs: A Case Study of Cache and Network Layer

“…Some techniques aim to reduce the number of active ways accessed in each cache access to the number of ways halted in the case of a miss prediction using software or hardware. Other techniques reconfigure cache using computer software [43], while some techniques predict the program behaviour [3,41,42,[44][45][46]. Some techniques deal with instructions in the cache [3,15,16,41,[47][48][49][50][51][52].…”

“…Mallya et al [46] proposed a way halted prediction cache as an energy-efficient cache architecture for embedded processors. The technique aims to reduce the number of active ways to one in case the prediction is a hit and active ways to the number of ways halted in case of a miss prediction.…”

A Survey of Emerging Architectural Techniques for Improving Cache Energy Consumption

“…Neethu et al [60] proposed a way halted prediction cache as an energy-efficient cache architecture for embedded processors. The technique aims to reduce the number of active ways to one in case the prediction being a hit and active ways to the number of ways halted in case of a miss prediction.…”