Wavelet-based phase classification

Huffmire, Ted; Sherwood, Timothy

doi:10.1145/1152154.1152172

Cited by 30 publications

(24 citation statements)

References 33 publications

(31 reference statements)

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“…We use signal analysis techniques in a similar fashion compared to prior work [9], [12] to allow us to capture micro-architecture independent application characteristics.…”

Section: B Determining Application Periodicitymentioning

confidence: 99%

Sampled simulation of multi-threaded applications

Carlson

Heirman

Eeckhout

2013

2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Abstract-Sampling is a well-known workload reduction technique that allows one to speed up architectural simulation while accurately predicting performance. Previous sampling methods have been shown to accurately predict single-threaded application runtime based on its overall IPC. However, these previous approaches are unsuitable for general multi-threaded applications, for which IPC is not a good proxy for runtime. Additionally, we find that issues such as application periodicity and inter-thread synchronization play a significant role in determining how best to sample these applications.The proposed multi-threaded application sampling methodology is able to derive an effective sampling strategy for candidate applications using architecture-independent metrics. Using this methodology, large input sets can now be simulated which would otherwise be infeasible, allowing for more accurate conclusions to be made than from studies using scaled-down input sets. Through the use of the proposed methodology, we can simulate less than 10% of the total application runtime in detail. On the SPEComp, NPB and PARSEC benchmarks, running on an 8-core simulated system, we achieve an average absolute error of 3.5%.

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“…We use signal analysis techniques in a similar fashion compared to prior work [9], [12] to allow us to capture micro-architecture independent application characteristics.…”

Section: B Determining Application Periodicitymentioning

confidence: 99%

Sampled simulation of multi-threaded applications

Carlson

Heirman

Eeckhout

2013

2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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“…The authors in [16] and [22] list, describe and compare these techniques. In all of these classifications different high-level statistics are used to describe the similarity of samples: instruction mix, loop detection, memory access addresses etc.…”

Section: Related Workmentioning

confidence: 99%

Accurate off-line phase classification for HW/SW co-designed processors

Brankovic

Stavrou

Gibert

et al. 2014

Proceedings of the 11th ACM Conference on Computing Frontiers

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Evaluation techniques in microprocessor design are mostly based on simulating selected application's samples using a cycle-accurate simulator. These samples usually correspond to different phases of the application stream. To identify these phases, relevant high-level application statistics are collected and clustered using a process named "Off-Line Phase Classification". The purpose of phase classification is to reduce the number of samples that need to be simulated with the minimum loss in accuracy (compared to simulating the complete set of samples).Unfortunately, when directly applied to HW/SW co-designed processors 1 the traditional phase classifications do not provide a good trade-off between accuracy and the number of samples. As an example, according to our experimental results, to achieve a 4% error (compared to simulating all the samples) one needs to simulate 2.5X more samples for the case of HW/SW co-designed processors compared to what is necessary for HW-only processors.In this paper, we propose a novel off-line phase classification scheme called TOL Description Vector (TDV), which is suitable for HW/SW co-designed processors. TDV targets at estimating the TOL particularities and on average gives significantly better accuracy than traditional phase classification for any number of selected samples. For instance, TDV reaches the average error of 3% with 3X less samples than traditional classification. These benefits apply for different TOL and microarchitecture configurations.

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“…The transform has been used to reduce post-mortem trace volume [9], and its output has been analyzed to extract program phase behavior [7,18] and program structure [8]. Our tool differs from these in that it performs a parallel wavelet transform at runtime instead of in a post-mortem analysis step.…”

Section: Related Workmentioning

confidence: 99%

Scalable load-balance measurement for SPMD codes

Gamblin

Supinski

Schulz

et al. 2008

2008 SC - International Conference for High Performance Computing, Networking, Storage and Analysis

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Good load balance is crucial on very large parallel systems, but the most sophisticated algorithms introduce dynamic imbalances through adaptation in domain decomposition or use of adaptive solvers. To observe and diagnose imbalance, developers need system-wide, temporally-ordered measurements from full-scale runs. This potentially requires data collection from multiple code regions on all processors over the entire execution. Doing this instrumentation naively can, in combination with the application itself, exceed available I/O bandwidth and storage capacity, and can induce severe behavioral perturbations.We present and evaluate a novel technique for scalable, low-error load balance measurement. This uses a parallel wavelet transform and other parallel encoding methods. We show that our technique collects and reconstructs systemwide measurements with low error. Compression time scales sublinearly with system size and data volume is several orders of magnitude smaller than the raw data. The overhead is low enough for online use in a production environment.

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Wavelet-based phase classification

Cited by 30 publications

References 33 publications

Sampled simulation of multi-threaded applications

Sampled simulation of multi-threaded applications

Accurate off-line phase classification for HW/SW co-designed processors

Scalable load-balance measurement for SPMD codes

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