Watershed parallel algorithm for asynchronous processors array

Galilée, Bruno; Mamalet, Franck; Renaudin, Marc; Coulon, Pierre-Yves

doi:10.1109/icme.2002.1035901

Cited by 6 publications

(4 citation statements)

References 2 publications

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“…It is shown that the actual flooding is accomplished by a single instruction in a wavepropagating manner. The achieved results are comparable to application specific arrays [6,11] In general, we can see that an appropriate decomposition of complex algorithms into simple operations can provide a significant performance increase when implemented on the proposed architecture.…”

Section: Watershed Transformsupporting

confidence: 53%

Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing

Lopich

Dudek

2006 IEEE International Symposium on Circuits and Systems

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Abstract-This paper describes a new architecture for a cellular processor array integrated circuit, which operates in both discreteand continuous-time domains. Asynchronous propagation networks, enabling trigger-wave operations, distance transform calculation, and long-distance inter-processor communication, are embedded in an SIMD processor array. The proposed approach results in an architecture that is efficient in implementing both local and global image processing algorithms.

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Section: Watershed Transformsupporting

confidence: 53%

Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing

Lopich

Dudek

2006 IEEE International Symposium on Circuits and Systems

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“…[14], due to known optimizations applied to the sequential algorithm and corrections done on the parallel one. In a fine grain configuration, our system is able to segment about 60,000 QCIF images per second, that is to say a speedup factor close to 10,000.…”

Section: Complexity Estimationmentioning

confidence: 99%

“…A description of this asynchronous version of the "HillClimbing" algorithm was previously presented in [14], and will be detailed in Section 2. This paper then focuses on the formal proof of the algorithm correctness (Section 3).…”

Section: Introductionmentioning

confidence: 99%

Parallel Asynchronous Watershed Algorithm-Architecture

Galilee

Mamalet

Renaudin

et al. 2007

IEEE Trans. Parallel Distrib. Syst.

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A joint algorithm-architecture study has resulted into a new version of a picture segmentation system complying with multimedia mobile terminal constraints, i.e., real-time computing, and low power consumption. Previously published watershed segmentation algorithms required at least three global synchronization points: minima detection, labeling and flooding. This paper presents a new fully asynchronous algorithm, where pixels can compute their local data in parallel and independently from one another, and which requires only a unique final global synchronization point. This paper provides a formal demonstration of the convergence and correctness of this new parallel asynchronous algorithm using a mathematical model of data propagation in a graph: the associative net formalism. We demonstrate the simplicity of implementation of this algorithm on parallel processor arrays. We explore, simulate, and validate several configurations of the algorithm-architecture using a "SystemC" model. Simulations reveal an image segmentation rate up to 66,000 QCIF images/sec, i.e., a speed-up factor of more than 1,000 times compared with state of the art watershed algorithms. A fine grain processor array design using STmicroelectronics 0:18m CMOS technology confirms that this new approach is a breakthrough in the domain of real-time image segmentation.

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“…Several algorithms were proposed [13,14]. They consider a topographical representation of the image, where the altitude is given by the grey level of each pixel.…”

Section: Watershed Segmentationmentioning

confidence: 99%

An architecture based on reconfigurability and asynchronism for real-time image processing

Denoulet

Merigot

2007

J Real-Time Image Proc

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This paper presents the evolution of the Associative Mesh, a massively parallel SIMD architecture based on reconfigurability and asynchronism. To favor its System on Chip implementation, we introduce a reorganization of the structure based on processors virtualization and evaluate its consequences on hardware cost and algorithmic performances. Using an evaluation environment based on a programming library and a parameterized description of the architecture, we show that a virtualized Associative Mesh achieves real-time execution for a number of complex image processing algorithms, including split and merge segmentation, watershed segmentation and motion detection.

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Watershed parallel algorithm for asynchronous processors array

Cited by 6 publications

References 2 publications

Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing

Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing

Parallel Asynchronous Watershed Algorithm-Architecture

An architecture based on reconfigurability and asynchronism for real-time image processing

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