Water-enhanced negative bias temperature instability in p-type low temperature polycrystalline silicon thin film transistors

Zhang, Meng; Zhou, Wei; Chen, Rongsheng; Wong, Man; Kwok, Hoi Sing

doi:10.1016/j.microrel.2013.07.082

Cited by 11 publications

(13 citation statements)

References 9 publications

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“…As shown in Fig. 3, the degradation slope is about 0.32, consistent to previous report [18]. It can be observed that under the same NBT stress, the proposed TFT with interlayer exhibits much more reliable characteristics.…”

Section: Resultssupporting

confidence: 89%

“…It can be observed that under the same NBT stress, the proposed TFT with interlayer exhibits much more reliable characteristics. The NBT stress [8], [18], which breaks the bonds at interface/GBs and generates dangling bonds, brings more interface/GB trap states and degenerates the device. Thus, the reliability test results reveal that the proposed TFT with interlayer possesses superior interface/GB quality.…”

Section: Resultsmentioning

confidence: 99%

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A Simple Method to Grow Thermal <inline-formula> <tex-math notation="TeX">${\rm SiO}_{2}$ </tex-math></inline-formula> Interlayer for High-Performance SPC Poly-Si TFTs Using <inline-formula> <tex-math notation="TeX">${\rm Al}_{2}{\rm O}_{3}$ </tex-math></inline-formula> Gate Dielectric

Zhang

Zhou

Chen

et al. 2014

IEEE Electron Device Lett.

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A simple method is proposed to grow thermal SiO 2 interlayer when performing solid-phase-crystallized (SPC) process. By employing such interlayer between SPC polycrystalline silicon channel and Al 2 O 3 gate dielectric, highperformance SPC thin-film transistors (TFTs) with field effect mobility of 67.80 cm 2 V s −1 and ON/OFF ratio of 2.31 × 10 8 at V ds = −0.1 V are achieved due to the superior interface quality and improved grain boundaries by the incorporation of excess Si interstitials. The TFT with interlayer also exhibits good reliability under negative bias temperature stress test.

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Section: Resultssupporting

confidence: 89%

Section: Resultsmentioning

confidence: 99%

A Simple Method to Grow Thermal <inline-formula> <tex-math notation="TeX">${\rm SiO}_{2}$ </tex-math></inline-formula> Interlayer for High-Performance SPC Poly-Si TFTs Using <inline-formula> <tex-math notation="TeX">${\rm Al}_{2}{\rm O}_{3}$ </tex-math></inline-formula> Gate Dielectric

Zhang

Zhou

Chen

et al. 2014

IEEE Electron Device Lett.

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“…For these high-performance BG poly-Si TFTs, hitherto no systematical reliability studies have been performed and reported. It has been identified for poly-Si TFTs that hot-carrier (HC) effect [10]- [14], self-heating (SH) effect [15]- [22], and negative bias temperature instability (NBTI) effect [23]- [27] are three key mechanisms inducing device degradation. In this paper, degradation of BG poly-Si TFTs under different kinds of dc stresses [HC stress, SH stress, and negative bias temperature (NBT) stress], is symmetrically investigated.…”

Section: Characterization Of Dc-stress-induced Degradation In Bridgedmentioning

confidence: 99%

“…9 shows comparisons of transfer curve degradation in normal poly-Si TFTs and BG poly-Si TFTs under NBT stress. Typical NBT degradation behaviors, negative V th shift and the degradation slope of 0.23 [1], [24], [26], [27], are observed, as shown in Fig. 9 and its right inset.…”

Section: B Self-heatingmentioning

confidence: 99%

Characterization of DC-Stress-Induced Degradation in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

Zhang

Zhou

Chen

et al. 2014

IEEE Trans. Electron Devices

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In this paper, dc-stress-induced degradation in bridged-grain (BG) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) is systemically characterized and investigated. Compared with normal poly-Si TFTs, BG poly-Si TFTs exhibit better hot-carrier (HC) reliability, better self-heating (SH) reliability, and better negative bias temperature (NBT) instability. Resulting from the heavily doped BG lines inside the active channel, lateral electric field reduction at the drain side, Joule heat diffusion enhancement at the channel length direction, and boron-hydrogen bond formation at interface/grain boundaries are, respectively, responsible for the improved HC reliability, SH reliability, and NBT reliability in BG poly-Si TFTs. In addition, stress V g -dependent HC degradation with fixed stress V d , stress power density-dependent SH degradation, and vertical electrical field-dependent NBT degradation are also examined in both normal poly-Si TFTs and BG poly-Si TFTs. All test results indicate that such high-performance and highly reliable BG poly-Si TFT has a great potential for system-on-panel application.Index Terms-Bridged grain (BG), hot carrier (HC), negative bias temperature instability (NBTI), polycrystalline silicon (poly-Si), self-heating (SH), thin-film transistors (TFTs).

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“…Low-temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) have been widely used for applications such as switches in active-matrix liquid crystal displays (AMLCDs) and active-matrix organic light emitting diodes (AMOLED) because of their high field effect carrier mobility, high driving current and uniformity of polycrystalline silicon (poly-Si) compared to conventional amorphous silicon (a-Si) [1,2]. In addition, further improvement in the performance of the poly-Si TFT can enable the integration of various functional devices, such as the memory and controller, on a glass panel to achieve system-onpanel (SOP) display.…”

Section: Introductionmentioning

confidence: 99%

Low-Temperature Poly-Si TFT Charge Trap Flash Memory with Sputtered ONO and Schottky Junctions

An¹,

Kim²

2015

Transactions on Electrical and Electronic Materials

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A charge-trap flash (CTF) thin film transistor (TFT) memory is proposed at a low-temperature process (≤ 450℃). The memory cell consists of a sputtered oxide-nitride-oxide (ONO) gate dielectric and Schottky barrier (SB) source/drain (S/D) junctions using nickel silicide. These components enable the ultra-low-temperature process to be successfully achieved with the ONO gate stacks that have a substrate temperature of room temperature and S/D junctions that have an annealing temperature of 200℃. The silicidation process was optimized by measuring the electrical characteristics of the Ni-silicided Schottky diodes. As a result, the Ion/Ioff current ratio is about 1.4×10 5 and the subthreshold swing and field effect mobility are 0.42 V/dec and 14 cm 2 /V·s at a drain voltage of -1 V, respectively.

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Water-enhanced negative bias temperature instability in p-type low temperature polycrystalline silicon thin film transistors

Cited by 11 publications

References 9 publications

A Simple Method to Grow Thermal <inline-formula> <tex-math notation="TeX">${\rm SiO}_{2}$ </tex-math></inline-formula> Interlayer for High-Performance SPC Poly-Si TFTs Using <inline-formula> <tex-math notation="TeX">${\rm Al}_{2}{\rm O}_{3}$ </tex-math></inline-formula> Gate Dielectric

A Simple Method to Grow Thermal <inline-formula> <tex-math notation="TeX">${\rm SiO}_{2}$ </tex-math></inline-formula> Interlayer for High-Performance SPC Poly-Si TFTs Using <inline-formula> <tex-math notation="TeX">${\rm Al}_{2}{\rm O}_{3}$ </tex-math></inline-formula> Gate Dielectric

Characterization of DC-Stress-Induced Degradation in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

Low-Temperature Poly-Si TFT Charge Trap Flash Memory with Sputtered ONO and Schottky Junctions

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