WASP: Selective Data Prefetching with Monitoring Runtime Warp Progress on GPUs

Oh, Yunho; Yoon, Myung Kuk; Park, Jong Hyun; Park, Yongjun; Ro, Won Woo

doi:10.1109/tc.2018.2813379

Cited by 4 publications

(3 citation statements)

References 22 publications

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“…• In pursuit of sustaining an error-free and optimal pipeline activity, the dispatch logic is altered. By monitoring the progress of the boosted warps [25], subsequent dependent warps are accordingly dispatched. This, in turn, alleviates scoreboarding and results in a better thread block performance.…”

Section: Circuit-architectural Considerations For Boostmentioning

confidence: 99%

“…• If a boosted warp is stalled due to any architectural hazard, it can incur a tremendous power overhead. To avoid this situation, a warp's execution time is tracked [25], and if the execution time crosses a threshold, the boost is disabled, i.e., the execution speed is reduced to the corresponding nominal value.…”

Section: Improving Energy-efficiencymentioning

confidence: 99%

“…A low-complexity heuristic is adopted (line 6 to 13 in Algorithm 1) to ascertain the critical warp(s). The progress of a warp is tracked using the existing dynamic load execution (DLE) counter in modern GPUs[25]. The DLE count gets incremented only if the warp has finished executing a load.…”

mentioning

confidence: 99%

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Predicting Critical Warps in Near-Threshold GPGPU Applications using a Dynamic Choke Point Analysis

Sanyal

Basu

Bal

et al. 2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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General-purpose graphics processing units (GPGPU), owing to their enormous parallelism have found ubiquitous applications in parallel computing. Along with an unprecedented performance offered by every new generation of the GPGPUs, their peak power rating has also increased over the years. As an inevitable consequence, Near-Threshold Computing (NTC) has come to the rescue, offering a substantially lower demand on the power supply unit, while striving to achieve a super-threshold performance, by exploiting a higher parallelism. However, a severe device-level delay variability arising from process variation (PV), can significantly diminish the NTC system performance. In this work, choke points-a unique device-level characteristic of PV at NTC-that can exacerbate the delays of the GPGPU parallel warps have been explored. In order to improve the NTC GPU performance, a family of holistic circuit-architectural solutions, referred to as Choke Point Aware Warp Speculator (CPAWS) has been proposed. CPAWS identifies the choke point induced critical warps in GPGPU applications, and improves their execution latencies in their respective execution units. Compared to a state-of-the-art warp scheduling policy, the best scheme improves the performance and energy-efficiency of an NTC GPU by ∼39% and ∼31%, respectively. while incurring marginal hardware overheads.

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Section: Circuit-architectural Considerations For Boostmentioning

confidence: 99%

Section: Improving Energy-efficiencymentioning

confidence: 99%