Warped-compression

Abstract

This paper presents Warped-Compression, a warp-level register compression scheme for reducing GPU power consumption. This work is motivated by the observation that the register values of threads within the same warp are similar, namely the arithmetic differences between two successive thread registers is small. Removing data redundancy of register values through register compression reduces the effective register width, thereby enabling power reduction opportunities. GPU register files are huge as they are necessary to keep concurrent execution contexts and to enable fast context switching. As a result register file consumes a large fraction of the total GPU chip power. GPU design trends show that the register file size will continue to increase to enable even more thread level parallelism. To reduce register file data redundancy warped-compression uses low-cost and implementationefficient base-delta-immediate (BDI) compression scheme, that takes advantage of banked register file organization used in GPUs. Since threads within a warp write values with strong similarity, BDI can quickly compress and decompress by selecting either a single register, or one of the register banks, as the primary base and then computing delta values of all the other registers, or banks. Warped-compression can be used to reduce both dynamic and leakage power. By compressing register values, each warp-level register access activates fewer register banks, which leads to reduction in dynamic power. When fewer banks are used to store the register content, leakage power can be reduced by power gating the unused banks. Evaluation results show that register compression saves 25% of the total register file power consumption. Bank ArbiterRegister Bank 0 Register Bank 31Operand Collector InterconnectRegister Bank 1

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“…Following the same goal, Lu et al 34 have recently proposed a low‐latency, hardware‐based compression architecture optimized for floating point data that reduces bandwidth demand and energy consumption by 44.46 % and 44.34 % , respectively. Focusing entirely on the register level, Lee et al 35 have explored register compression with the goal of reducing the energy consumption of graphics hardware. All approaches have in common that they are using custom, lightweight compression algorithms instead of general‐purpose algorithms and rely on custom hardware designs.…”