Wakeup-Free and Endurance-Robust Ferroelectric Field-Effect Transistor Memory Using High Pressure Annealing

Remote Oxygen Scavenging of the Interfacial Oxide Layer in Ferroelectric Hafnium–Zirconium Oxide-Based Metal–Oxide–Semiconductor Structures

“…Filling up of oxygen vacancies in orthorhombic crystal would cause depinning of FE grains and demonstrate an enhancement in polarization. The nature of the 2 P r in the nonscavenged and scavenged sample could originate from the internal depolarization field coupled with charge trapping/detrapping at the defect states at the FE-HZO/p+Si interface . Note that it is difficult to compare the two cases quantitatively due to the different thicknesses of the ILs.…”

“…The nature of the 2P r in the nonscavenged and scavenged sample could originate from the internal depolarization field coupled with charge trapping/ detrapping at the defect states at the FE-HZO/p+Si interface. 31 Note that it is difficult to compare the two cases quantitatively due to the different thicknesses of the ILs. Further investigation is required to understand the depolarization field's effect on the 2P r values of these samples.…”

“…This is because the thinning of IL should have a greater impact on gate leakage because gate leakage is sensitive to the amorphous low-k SiO 2 interlayer thickness and scavenging electrodes have been reported to increase gate leakage when compared to devices with thicker ILs. 31 To test the repeatability of the process, two sets of scavenging and nonscavenging electrode samples were fabricated and 5 devices on each sample were measured. The results are summarized in Figure 4d.…”

“…Conversely, the size of the depolarization field in the DE layer increases with thinning the IL thickness, or gettering process, as shown previously. 23 Given the need for reducing the write voltage in ferroelectric field-effect transistors, state-ofthe-art interfacial passivation techniques 31 can be employed to mitigate the adverse effects of remote scavenging to thin down the interfacial layer in these devices. ■ ASSOCIATED CONTENT * sı Supporting Information…”

Ferroelectric-Metal Field-Effect Transistor With Recessed Channel for 1T-DRAM Application

“…Although the voltage drop is enhanced and program voltage (VW) is reduced by thinning the SiO2, the electric field (e-field) across the SiO2 is still relatively high and comparable to the breakdown field of the SiO2 layer, which limits the program/erase (P/E) cycling endurance to < 10 6 [7][8][9][10][11]. In this regard, for the commercialization of FeFETs as 1T-DRAM, the e-field across the SiO2 IL (EIL) should be minimized to obtain robust endurance characteristics without sacrificing the voltage drop over the FE [12,13].…”