Wafer to wafer overlay control algorithm implementation based on statistics

Lee, Byeong Soo; Kang, Yongjoon; Hwang, Hyun Woo; Song, Min‐Kyu

doi:10.1117/12.2086936

Cited by 3 publications

(3 citation statements)

References 1 publication

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“…Given the overlay requirements for multi-patterning, stringent control of the pattern placement becomes even a greater challenge, with edge placement error (EPE) a key performance metric. In practice, EPEs carry contributions from various steps in IC layout design, mask fabrication, patterning tool operation, and pattern fabrication process 5 .…”

Section: Introductionmentioning

confidence: 99%

Lithographic imaging-driven pattern edge placement errors at 10nm node

et al. 2016

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Demand for ever increasing level of microelectronics integration continues unabated, driving the reduction of the integrated circuit critical dimensions, and escalating requirements for image overlay and pattern dimension control. The challenges to meet these demands are compounded by requirement that pattern edge placement errors be at single nanometer levels. Layout design together with the patterning tools performance play key roles in determining location of the pattern edges at different device layers. However, complexities of the layout design often lead to stringent tradeoffs for viable optical proximity correction and imaging strategy solutions. As a result, in addition to scanner overlay performance, pattern imaging plays a key role in the pattern edge placement. The imaging contributes to edge displacement by impacting the image dimensions and by shifting the images relative to their target locations. In this report we discuss various aspects of advanced image control at 10 nm integrated circuit design rules. We analyze the impact of pattern design and scanner performance on pattern edges. We present an example of complex, three step litho-etch patterning involving immersion scanners. We draw conclusion on edge placement control when complex images interact with wafer topography.

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Section: Introductionmentioning

confidence: 99%

Lithographic imaging-driven pattern edge placement errors at 10nm node

et al. 2016

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“…In recent years, scaling could no longer be achieved by reducing exposure-tool wavelength, because immersion lithography at 193 nm (193i) is a practical limit to deep ultraviolet imaging, and extreme ultraviolet (EUV) lithography has been delayed. 5 Figure 1 spotlights various EPEs common during pattern imaging and points out what are some of the fabricated pattern excursion from the target locations defined by the pattern design intent. [1][2][3] Using 193i, the devices are built layer-by-layer with the number of layers in advanced designs continuing to grow.…”

Section: Introductionmentioning

confidence: 99%

Lithographic imaging-driven pattern edge placement errors at the 10-nm node

Tyminski

Sakamoto

Palmer

et al. 2016

J. Micro/Nanolith. MEMS MOEMS

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As new microelectronic designs are being developed, the demands on image overlay and pattern dimension control are compounded by requirements that pattern edge placement errors (EPEs) be at a single-nanometer levels. Scanner performance plays a key role in determining location of the pattern edges at different device layers, not only through overlay but also through imaging performance. The imaging contributes to edge displacement through the variations of the image dimensions and by shifting the images from their target locations. We discuss various aspects of advanced image control relevant to a 10-nm node integrated circuit design. We review a range of issues of pattern edge placement directly linked to pattern imaging. We analyze the impact of different pattern design and scanner-related edge displacement drivers. We present two examples of imaging strategies to pattern logic device metal layer cuts. We analyze EPEs of the cut images resulting from optimized layout design and scanner setup, and we draw conclusions on edge placement control versus imaging performance requirements. Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 06/24/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx J. Micro/Nanolith. MEMS MOEMS 021402-8 Apr-Jun 2016 • Vol. 15(2) Tyminski et al.: Lithographic imaging-driven pattern edge placement errors at the 10-nm node Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 06/24/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx J. Micro/Nanolith. MEMS MOEMS 021402-10 Apr-Jun 2016 • Vol. 15(2) Tyminski et al.: Lithographic imaging-driven pattern edge placement errors at the 10-nm node Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 06/24/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

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“…[3][4][5] Also the metrology targets are optimized 6 to minimize image placement discrepancy of the target grating with the device pattern. Several enhancement technologies such as high-order wafer alignment, (intrafield) high-order process correction [(i)HOPC], and correction per exposure are applied to the photo equipment and the process control system.…”

Section: Introductionmentioning

confidence: 99%

High-order distortion control using a computational prediction method for device overlay

Kang

Affentauschegg

Mulkens

et al. 2016

J. Micro/Nanolith. MEMS MOEMS

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Sung Kwon, "High-order distortion control using a computational prediction method for device overlay,"Abstract. As a result of the continuously shrinking features of the integrated circuit, the overlay budget requirements have become very demanding. Historically, overlay has been performed using metrology targets for process control, and most overlay enhancements were achieved by hardware improvements. However, this is no longer sufficient, and we need to consider additional solutions for overlay improvements in process variation using computational methods. In this paper, we present the limitations of third-order intrafield distortion corrections based on standard overlay metrology and propose an improved method which includes a prediction of the device overlay and corrects the lens aberration fingerprint based on this prediction. For a DRAM use case, we present a computational approach that calculates the overlay of the device pattern using lens aberrations as an additional input, next to the target-based overlay measurement result. Supporting experimental data are presented that demonstrate a significant reduction of the intrafield overlay fingerprint.

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Wafer to wafer overlay control algorithm implementation based on statistics

Cited by 3 publications

References 1 publication

Lithographic imaging-driven pattern edge placement errors at 10nm node

Lithographic imaging-driven pattern edge placement errors at 10nm node

Lithographic imaging-driven pattern edge placement errors at the 10-nm node

High-order distortion control using a computational prediction method for device overlay

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