2018
DOI: 10.1002/pssa.201800234
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Wafer‐Scale Nanoimprint Lithography Process Towards Complementary Silicon Nanowire Field‐Effect Transistors for Biosensor Applications

Abstract: The authors present a combined, p-and n-type fabrication process for silicon nanowire field-effect transistor (SiNW FET) biosensors on a 4" wafer format with nanowire widths down to 100 nm and a height of only 42 nm. The full wafer design includes various SiNW FET combinations with metal or electrolyte gate contacts. A top-down fabrication protocol on high-quality silicon-on-insulator wafers is developed. Down-thinning of Si is done by a modified CMOS cleaning solution, which gives the possibility to control t… Show more

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Cited by 11 publications
(18 citation statements)
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“…27 Depending on the dimensions of the SiO 2 hard mask, which we used in our processes, we got different values for absolute threshold voltages of the Si NW-ISFET sensors (compare Figures 2 and 4). 68 Nanowire structures comprise highly p-doped individual drains and a common source contact, which are etched out of the top silicon layer of the SOI wafers. The nanowire regions of typically 15 μm length and 100–200 nm width are left intrinsic and depending on the thickness of the silicon (40–60 nm) are either fully or partly depleted, which leads to the accumulation type transistor characteristics.…”
Section: Materials and Methodsmentioning
confidence: 99%
See 2 more Smart Citations
“…27 Depending on the dimensions of the SiO 2 hard mask, which we used in our processes, we got different values for absolute threshold voltages of the Si NW-ISFET sensors (compare Figures 2 and 4). 68 Nanowire structures comprise highly p-doped individual drains and a common source contact, which are etched out of the top silicon layer of the SOI wafers. The nanowire regions of typically 15 μm length and 100–200 nm width are left intrinsic and depending on the thickness of the silicon (40–60 nm) are either fully or partly depleted, which leads to the accumulation type transistor characteristics.…”
Section: Materials and Methodsmentioning
confidence: 99%
“…The etching profile results in trapezoid cross sections, 69 which are covered by a thin SiO 2 gate oxide of 6–8 nm in an almost wrapped around gate structure, which is partly still in contact with the BOX supporting the mechanic stability and giving the possibility for back gating. Typically, we fabricate devices with subthreshold swings of 100–120 mV/dec, 68 which is far away from the ideal values of about 60 mV/dec. Most likely, the quality of the gate oxide could be further improved by annealing in forming gas to decrease the subthreshold slope values.…”
Section: Materials and Methodsmentioning
confidence: 99%
See 1 more Smart Citation
“…An ultra-thin layer of oxide was grown on top of the SiNW to create the gate dielectric layer. A thick passivation layer was deposited on the source and the drain contact to enable the device to work reliably when interfacing with the liquid environment [ 6 , 13 , 22 , 25 , 26 , 27 , 28 , 29 , 30 ]. Each fabrication step induces variations that may alter the electronic characteristic from device to device.…”
Section: Introductionmentioning
confidence: 99%
“…Several different approaches can be found for nanoimprinting, being the main ones thermal NIL and UV NIL. In recent years a strong industrially-driven research can be observed, pushing NIL and its applications from purely academic purposes to innovations in data storage, point of care diagnostics, electronic and graphene devices or augmented reality [ 4 , 5 , 6 , 7 , 8 , 9 ]. With this shift, new materials need to be developed with properties that are compatible with mass production: fast curing and imprinting, robustness, reproducibility, and patterning on flexible substrates, both, at the micro and nano scale.…”
Section: Introductionmentioning
confidence: 99%