Wafer-Level-Probing Electrical Properties of Planar Junctionless Poly-Si Thin-Film Transistors Using a Novel C-V Charcacterization Scheme

Chuang, Chen-Fu; Peng, Kuanjun; Chang, Yu‐Chia; Lin, Hong‐Cheu; Li, P.W.

doi:10.7567/ssdm.2018.ps-10-14

Extended Abstracts of the 2018 International Conference on Solid State Devices and Materials 2018

DOI: 10.7567/ssdm.2018.ps-10-14

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Wafer-Level-Probing Electrical Properties of Planar Junctionless Poly-Si Thin-Film Transistors Using a Novel C-V Charcacterization Scheme

Chen-Fu Chuang¹,

Kuanjun Peng²,

Yu‐Chia Chang³

et al.

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Wafer-Level-Probing Electrical Properties of Planar Junctionless Poly-Si Thin-Film Transistors Using a Novel C-V Charcacterization Scheme

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