2009
DOI: 10.1016/j.proche.2009.07.383
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Wafer level packaging technology for silicon resonators

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Cited by 9 publications
(6 citation statements)
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“…The tuning fork resonators were fabricated on silicon-on-insulator (SOI) wafers. Their mode of operation and functional layout were based on resonators presented by CSEM previously [15][16] [17]. The fork tines were patterned into the device layer by deep reactive ion etching (DRIE).…”
Section: Resonator Design Fabrication and Characterizationmentioning
confidence: 99%
“…The tuning fork resonators were fabricated on silicon-on-insulator (SOI) wafers. Their mode of operation and functional layout were based on resonators presented by CSEM previously [15][16] [17]. The fork tines were patterned into the device layer by deep reactive ion etching (DRIE).…”
Section: Resonator Design Fabrication and Characterizationmentioning
confidence: 99%
“…[31][32][33] The fork tines were patterned into the device layer by deep reactive ion etching. Their mode of operation and functional layout were based on resonators previously presented by CSEM.…”
Section: Resonator Design Fabrication Andmentioning
confidence: 99%
“…Technologies for integration and vacuum tight and reliable packaging of these specific devices have been elaborated [50]. Recently, a novel technology for metallization of polymers (e.g.…”
Section: Miniature Sensorsmentioning
confidence: 99%