2014
DOI: 10.7735/ksmte.2014.23.3.230
|View full text |Cite
|
Sign up to set email alerts
|

Wafer Level Package Design Optimization Using FEM

Abstract: ARTICLE INFO ABSTRACTArticle history:Wafer level package technology is added to the surface of wafer circuit packages to create a semiconductor technology that can minimize the size of the package. However, in conventional packaging, warpage and fracture are major concerns for semiconductor manufacturing. We optimized the wafer dam design using a finite element method according to the dam height and heat distribution thermal properties. The dam design influences the uniform deposition of the image sensor and p… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

0
0
0

Publication Types

Select...

Relationship

0
0

Authors

Journals

citations
Cited by 0 publications
references
References 10 publications
0
0
0
Order By: Relevance

No citations

Set email alert for when this publication receives citations?