Wafer-level integration for hybrid chip of infrared detectors

Abstract

A large format, high density integration, high-performance infrared detectors are used in a wide range of imaging applications. However, it is difficult to fabricate a hybrid chip of a high performance infrared detector because of the low flip-chip bonding and under-fill process yields. In this work, the large format hybrid chip fabrication process with wafer level integration schemes is presented. In particular, the structure of the fabricated hybrid chip and the method of fabrication a hybrid chip by Au-to-Au bonding. Finally, the result of a hybrid chip made of pixel pitch 20μm is presented.