Wafer dicing process optimization and characterization for C90 low-k wafer technology

Abstract

This paper presents an investigation on the effect and optimization of machining parameters for 90nm low-k wafer topside peeling improvement in mechanical dicing operation. It is part of the continuous improvement that performed based on current established dicing recipe. The resulted outcomes to achieve are cut quality improvement, dicing yield loss reduction and device reliability enhancement for low-k wafer dicing. The experimental studies were conducted under varying table speed, Z1 spindle rotation as well as the Z1 cut depth was examined. The settings of machining parameters were determined by using design of experiment (DOE) techniques and the critical process parameters were determined and analyzed statistically by using analysis of variance (ANOVA). Optical visual inspection was conducted on post-processed low-k test wafers and several of scribe structures which comprised of different level of metal density, for a through quantification and categorization on the peeling mode. Worst case peeling measurements and characterizations were conducted by using optical microscope, scanning electron microscopy (SEM) and focused ion beam (FIB). Electrical test and device reliability assessments were conducted to reflect and confirm the improvement of the samples diced with optimized mechanical dicing process. As a result, the optimum dicing parameters to apply in production environment was realized and established in order to overcome the quality obstacles and yield loss issue in low-k wafer dicing.

Fabrication of a micro-cantilever gold plated beams array

“…In this work, dicing was done using the Loadpoint Micro Ace Series 3 dicing saw machine (Shi et al, 2009). Before the dicing, the wafer surface was coated with a layer of photoresist to protect the devices from the damage and contamination of the debris generated during the dicing process.…”