Wafer deposition/metallization and back grind, process-induced warpage simulation

Irving, S.; Liu, Youg

doi:10.1109/ectc.2003.1216487

Cited by 8 publications

(7 citation statements)

References 3 publications

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“…The thermal loading process was modeled by imposing a spatially uniform temperature change on the wafer. ''Element birth and death'' approach was employed to model the deposition of each layer [4]. For example, the solder ball is not involved in the deposition of PI and Cu, therefore in the simulation it was de-activated in the PI curing process, and activated until the solder reflow process cooled to 220°C.…”

Section: Finite Element Analysismentioning

confidence: 99%

“…von Silfhout and Irving investigated the warpage origination in back-end process using numerical calculation and verified by experiments [4,5]. Related warpage behaviors such as bifurcation and gravitational effects have also been studied [6].…”

Section: Introductionmentioning

confidence: 98%

“…Because PI and Cu have very different coefficient of thermal expansion (CTE) with silicon substrate, large thermal stresses and wafer warpage will be induced after the thermal process. After wafer thinning, the warpage tends to be more serious [4]. Large wafer warpage may result in failures during packaging processes including automatic handling, photolithography, and wafer dicing.…”

Section: Introductionmentioning

confidence: 98%

See 2 more Smart Citations

A novel mechanical diced trench structure for warpage reduction in wafer level packaging process

Zhu

et al. 2015

Microelectronics Reliability

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Section: Finite Element Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 98%

See 1 more Smart Citation

A novel mechanical diced trench structure for warpage reduction in wafer level packaging process

Zhu

et al. 2015

Microelectronics Reliability

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“…Wafer warpage research on single IC today is rather fruitful [1][2][3][4][5]. In fact, warpage issues involved not only that of single IC wafer but also multiple wafers with bonding [6] [7].…”

Section: Introductionmentioning

confidence: 99%

Warpage and stress optimization of wafer-level package of MEMS with glass frit bonding

Zhu

et al. 2014

2014 15th International Conference on Electronic Packaging Technology

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Warpage issue of wafer level package (WLP) has caught the attention of WLP industry. This paper aims at the warpage characteristics and optimization of the WLP (consisting of silicon MEMS wafer and silicon cover wafer) with glass frit bonding. Finite-element method (FEM) was used to study the warpage and stress optimization of the Si-Si bonding WLP. Some factors which affect WLP warpage, such as CTE (coefficient of thermal expansion) and Young's modulus of glass frit, ring thickness & width of glass frit and bonding temperature etc. were optimized. The stress of WLP was also calculated and the reliability level of the MEMS device was estimated. It turned out that CTE and Young modulus of glass frit are the key parameters for decreasing WLP warpage and stress and promoting the MEMS WLP. Ring width of glass frit and the thickness of silicon cover plate wafer have little impacts on WLP stress and warpage. With the optimized parameters taken into account, the stress in MEMS WLP falls down. Those optimization results have been put into actual WLP manufacture. Keywords-warpage; stress; optimization; glass frit; wafer level package (WLP); finite-element method (FEM); MOS (multi-beam optical sensor) deformation measurement; micro electro mechanical systems (MEMS)

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“…In the late 20th century, wafer warp research focused on semiconductor integrated circuit wafer [1][2][3]. Since the 21st century, with the increase of micro system integration, WLP developed fast and is becoming a hot spot of today's microelectronic packaging.…”

Section: Introductionmentioning

confidence: 99%

Warpage characteristics of wafer-level package of MEMS with glass frit bonding

Wang

Zhu

et al. 2013

2013 14th International Conference on Electronic Packaging Technology

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Warpage is one of the challenging problems for wafer level package (WLP). Especially, the bonding process of multiple wafers will bring additional stress to WLP and warpage of WLP. This paper aims at the stress and warpage characteristics of the WLP (consisting of silicon cover wafer and silicon MEMS wafer) with glass frit bonding. The finite element (FE) method and MOS (Multi-beam Optical Sensor) technology were used. Simulation result indicated that WLP presents almost zero warpage. MOS measurement result indicated that WLP actually presents convex warpage instead of zero warpage. It turned out that the convex warpage results from the temperature difference between WLP wafers (i.e. cover wafer and MEMS wafers) in the course of post-bond cooling. Taken the temperature difference into account, the simulation result was consistent with experiment results. Furthermore, on the basis of the convex warpage value the stress of WLP was also calculated so as to understand the stress distribution and estimate the reliability level of the MEMS device. Keywords-warpage,wafer level package(WLP), finite element method(FEM), micro Electro mechanical systems(MEMS), multibeam optical sensor (MOS)

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Wafer deposition/metallization and back grind, process-induced warpage simulation

Cited by 8 publications

References 3 publications

A novel mechanical diced trench structure for warpage reduction in wafer level packaging process

A novel mechanical diced trench structure for warpage reduction in wafer level packaging process

Warpage and stress optimization of wafer-level package of MEMS with glass frit bonding

Warpage characteristics of wafer-level package of MEMS with glass frit bonding

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