Wafer-Area-Saving Test Structures and Measurement Method for the Characterization of Interconnect Resistance and Capacitance in Nanometer Technologies

Abstract

Interconnect parasitic parameters are the dominant source for delay and noise in modern integrated circuits. Aggressive technology scaling has led to much higher resistance and larger coupling capacitance on interconnect. To predict the impact of interconnect to the circuit performance by accurately extracting electrical parameters of interconnect for circuit simulation, a novel test structure and an effective measurement method, which consumes less wafer area and hence results in lower production cost, are proposed in this paper. The method could be easily implemented for device characterization for DFM (design-for-manufacturing) applications.