Voltage scaling and dark silicon in symmetric multicore processors

Abstract

As technology scales further, multicore and many-core processors emerge as an alternative to keep up with performance demands. However, because of power and thermal constraints, we are obliged to power off remarkable area of chip. Many innovative techniques have been presented to improve energy efficiency and maintain utilization at the highest level. In this paper, we discuss different models and methods of exploiting dark silicon, and by using dynamic voltage and frequency scaling in Amdahl's law and considering memory overheads, we attempt to decrease amount of dark silicon and improve performance and performance per watt/joule. We propose high-performance and energy-efficient multicore architectures for variety of parallelisms and memory-intensities in workloads. According to the results, by voltage scaling, for a highly parallel CPU-intensive workload, we reach improvements of approximately 5.2× and 3.78× in performance per watt and performance per joule, respectively, while about 27 % reduction of performance should be tolerated. For memory-intensive applications, a negligible change in speedup is detected by scaling, while performance per watt and performance per joule for both serial and parallel applications lead to around 6× enhancements.

Exploração do Projeto de Sistemas Baseados em GPU ciente de Dark Silicon

“…Entretanto, Dennard [Dennard et al 2007] e outros já relataram que projetos de circuitos com transistores fabricados em processos tecnológicos abaixo de 90nm, não seguem a escala original, devido ao efeito exponencial da corrente de fuga, o que acaba por aumentar a densidade de potência e potência dissipada total do chip. Dessa forma, originalmente, esses projetos contêm regiões que não poderão estar ativas (em frequência máxima) concomitantemente com o restante do circuito [Nejatollahi and Salehi 2015, Shafique et al 2014, esse efeitoé denominado utilization wall. Aárea do chip que deve ser mantida "desligada" ou funcionando em frequência aquém do esperadoé denominada dark silicon [Hardavellas et al 2011].…”

System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation

“…Such a simulation can be realized only with an effective delay model. [13][14][15] Thus, a simple and relatively accurate system-level delay model which can be used in a multi supply voltage design 1 optimization is needed. This delay model can be used to estimate the core performance under different simulation conditions.…”