Voltage-island driven floorplanning considering level-shifter positions

Yu, Bei; Dong, Sheqin; Goto, Satoshi; Chen, Song

doi:10.1145/1531542.1531558

Cited by 10 publications

(22 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To make the comparisons more fairly, the same power model of switch and interconnection is used as [8]. Core power is evaluated according to (2) in Section 4, while the power of voltage level converters is evaluated according to (5).…”

Section: Resultsmentioning

confidence: 99%

“…Each voltage domain is called a Voltage Island (VI). By assigning lower voltage to some VIs, the total power can be reduced [2]. Some works applied MSV to NoC design to optimize the total power [1,14,15].…”

Section: Introductionmentioning

confidence: 99%

“…First, voltage level assignment is the key part in low power ASNoC design, as the voltage level can greatly influence the power consumption and performance of chip. Previous works proposed many methods to assign the best supply voltage from multiple alternative levels of each core according to performance and resource constraint in SoC [2][3][4][5]. However, these methods cannot be directly applied to ASNoC design.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Voltage island-driven power optimization for application specific network-on-chip design

Wang

Dong

Goto

2012

Proceedings of the Great Lakes Symposium on VLSI

Self Cite

View full text Add to dashboard Cite

In this paper, a voltage island aware framework is proposed for low power design of application specific NoC (LPASNoC). Through a three-phase processing including voltage island generation, VI-driven floorplanning and post-floorplan processing, the total power consumption, design cost and total wire length can be optimized. Experimental results show that compared to traditional ASNoC, the proposed method can reduce total core power by about 34.5% and chip area by about 26.8% without increasing communication power.

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Voltage island-driven power optimization for application specific network-on-chip design

Wang

Dong

Goto

2012

Proceedings of the Great Lakes Symposium on VLSI

Self Cite

View full text Add to dashboard Cite

show abstract

“…In contrast, Yu et al [11] did voltage assignemt and LS placement during floorplaning. Given a floorplan candidate, the positions and connections of modules were fixed.…”

Section: Motivationsmentioning

confidence: 99%

“…But few of them actually consider the LS placement, which makes the generated results may limit the potential applications. Yu et al [11] first considers the LS placement problem during floorplanning. For each candidate solution, the voltage assignment and level shifter placement are carried out.…”

Section: Introductionmentioning

confidence: 99%

Level shifter planning for timing constrained multi-voltage SoC floorplanning

Chu

Xia

Wang

2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

View full text Add to dashboard Cite

To implement multi-voltage technique in SoC designs, level shifters (LSs) are essential modules which translate signals among different voltage domains. However, inserting LSs requires nonnegligible area and timing overhead. In this paper, we study LS planning (LSP) method for timing constrained multi-voltage SoC floorplanning problem. The design flow consists of two phases. In phase I, to reserve the desired white space for the placement of LSs, the netlist is modified by assigning virtual LSs in the nets. In phase II, the main floorplanning loop is implemented. Different from previous works which do voltage assignment without physical information feedback, we build an inner loop between voltage assignment and LS placement under the constraints of both timing and physical layout. Experimental results on Gigascale Systems Research Center (GSRC) benchmark suites indicate the proposed approach can improve power saving by 15% with 4% area increase.

show abstract