Volcano-shaped field emitters for large area displays

Fabrication of gated SiC vertical edge emitters by chemical mechanical polishing

“…Figure 11 shows the emission current versus gate voltage characteristics of devices with gate post dimensions of 6, 9, 15, 25, and 50 µm and corresponding SiC emitter rim peripheries of about 30, 40, 60, 96, and 176 µm, respectively, measured at a pressure of 3 × 10 −8 Torr, a collector voltage of 2000 V, and a collector-to-emitter distance of 0.5 cm. The turn-on-voltages at 1 nA collector current range from about 180 to 260 V, which is similar to the values reported for Au emitters of similar shapes with 1 µm gate-to-emitter separation [5]. The collector current increases with increasing emitter periphery, but starts to saturate at higher gate voltages and for the 9 and 50 µm devices actually decreases.…”

“…Dominant emitters within the array produce a larger local voltage drop which reduces their gate voltage and thus let the lesser emitters contribute to the total current of the ensemble. In addition to cone emitters, gated vertical emitters are being considered [4][5][6]. These devices offer the advantage that expensive, fine line lithography does not have to be used in manufacturing.…”

“…These devices offer the advantage that expensive, fine line lithography does not have to be used in manufacturing. Single-gated devices using Cr, and Au have been reported in [5], and a doublegated device has been proposed in [6]. To obtain uniform emission, it is still necessary to provide a resistive path for these devices within an array.…”

Field Emission Flat Panel Displays

“…7.7, and the SEM micrograph of a TiW-Au emitter is shown in Fig. 7.8 [10]. By stepping the oxide near the gate plateau, the turn-on voltage can be reduced without increasing the gate-to-emitter capacitance significantly.…”

“…diagonal prototype with 240 × 240 × 3 pixels and 8.6-mm panel spacing has been demonstrated using stripe-patterned P-22 (R/G/B) phosphors and a FIGURE 7.7. Cross section of a single gated edge emitter using a stepped oxide approach to reduce the gate-to-emitter distance near the emission area without significantly increasing device capacitance [10].…”