Voiding and Thermal Resistance Modeling and Characterization for a QFN Assembly

Abstract

Quad Flatpack No lead (QFN) packages have become a popular choice in electronics packaging due to its small form factor. They are also gaining rapid industry acceptance because of its excellent thermal and electrical performance. The bottom side of the QFN package has a large thermal pad. This exposed die attach pad effectively conducts heat to the PCB and also provides a stable ground connection. Effective soldering of this surface to the pad on the PCB is required for good thermal dissipation and component functionality. The exposed thermal pad presents various challenges during the surface mount assembly process. One major challenge is solder void formation. Voids are primarily formed due to the entrapment of volatiles in flux outgassing during the reflow process. The primary objective of this study is to determine optimal parameters to minimize void formation in QFN packages (QFN16, QFN20, QFN28, QFN32 and QFN44), specifically the reflow profile, lead-free solder paste and stencil aperture opening for the thermal pad. A systematic Design of Experiments (DOE) based approach was used to arrive at conclusions, using the ratio of void volume on the thermal pad to the actual volume of solder paste printed, as the response variable. A theoretical thermal resistance response variable was also modeled to analyze the DOE parameters and the conclusions were similar to the void model. Various graphs are presented to understand the impact of different parameters. Interaction graphs are used to determine optimal settings for each parameter. A regression equation for relationship between the factors and the void volume is identified to predict void volumes for any given component, paste volume and paste transfer efficiency.