VMM1 - An ASIC for micropattern detectors

Geronimo, G. De; Fried, J.; Li, Shaorui; Metcalfe, J.; Nambiar, Neena; Vernon, E.; Polychronakos, V.

doi:10.1109/nssmic.2012.6551184

Cited by 30 publications

(44 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…VMM3 [3] is a mixed signal (analogue and digital) radiation tolerant ASIC numbering about 5.2 milion transistors in an area of 8384 µm × 15 308 µm. The ASIC is designed at Brookhaven National Laboratory and fabricated in the 130 nm Global Foundries 8RF-DM process.…”

Section: Vmm3 Asic Descriptionmentioning

confidence: 99%

Prototype board development for the validation of the VMM ASICs for the new small wheel ATLAS upgrade project

Gkountoumis

2018

2018 7th International Conference on Modern Circuits and Systems Technologies (MOCAST)

View full text Add to dashboard Cite

Abstract-The VMM is a custom Application Specific Integrated Circuit (ASIC) which was designed to be used in the frontend readout electronics of both micromegas (MM) and small Thin Gap Chambers (sTGC) detectors of the New Small Wheel (NSW) Phase-I upgrade project of the ATLAS experiment. A new version of the VMM was recently fabricated and for that reason various prototype boards, the micromegas Front-End (MMFE1) and the General Purpose VMM (GPVMM), have been fabricated and extensively tested in order to validate the functionality of the ASIC. These boards use commercial Field Programmable Gate Arrays (FPGAs) for direct communication with computers which is achieved through 10/100/1000 Mbps Ethernet and UDP/IP protocols. The low noise performance of these boards gave the opportunity to be used in various test beams with micromegas detectors for validating the VMM and for performance studies of the sTGC detectors. A detailed description of the boards along with the results of the test beam and the detector studies will be described.

show abstract

Section: Vmm3 Asic Descriptionmentioning

confidence: 99%

Prototype board development for the validation of the VMM ASICs for the new small wheel ATLAS upgrade project

Gkountoumis

2018

2018 7th International Conference on Modern Circuits and Systems Technologies (MOCAST)

View full text Add to dashboard Cite

show abstract

“…The FE boards contain a number of ASICs called VMMs [7] each providing trigger and tracking primitives for 64 detector channels. A second ASIC, the Read Out Controller (ROC) will aggregate, process and format the data generated by the VMM FE chips.…”

Section: Connectivitymentioning

confidence: 99%

Level-1 data driver card of the ATLAS new small wheel upgrade compatible with the phase II 1 MHz readout scheme

Gkountoumis

2016

2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST)

View full text Add to dashboard Cite

Abstract-The Level-1 Data Driver Card (L1DDC) will be designed for the needs of the future upgrades of the innermost stations of the ATLAS end-cap muon spectrometer. The L1DDC is a high speed aggregator board capable of communicating with a large number of front-end electronics. It collects the Level-1 data along with monitoring data and transmits them to a network interface through a single bidirectional fiber link. In addition, the L1DDC board distributes trigger, time and configuration data coming from the network interface to the front-end boards. The L1DDC is fully compatible with the Phase II upgrade where the trigger rate is expected to reach 1 MHz.This paper describes the overall scheme of the data acquisition process and especially the L1DDC board. Finally, the electronics layout on the chamber is also mentioned.

show abstract

“…Signals from up to 104 sTGC pads in a quadruplet are routed to two Amplifier-Shaper-Discriminator ASICs (ASD) [3]. The detector signals are converted to TimeOver-Threshold (TOT) pulses and processed by a pad TDS.…”

Section: Introductionmentioning

confidence: 99%

A programmable time alignment scheme for detector signals from the upgraded muon spectrometer at the ATLAS experiment

Wang

Guan

Chapman

et al. 2017

Nuclear Instruments and Methods in Physics Research Section A:

View full text Add to dashboard Cite

Abstract-We present a programmable time alignment scheme used in an ASIC for the ATLAS forward muon trigger development. The scheme utilizes regenerated clocks with programmable phases to compensate for the timing offsets introduced by different detector trace lengths. Each ASIC used in the design has 104 input channels with delay compensation circuitry providing steps of ~ 3 ns and a full range of 25 ns for each channel. Detailed implementation of the scheme including majority logic to suppress single-event effects is presented. The scheme is flexible and fully synthesizable. The approach is adaptable to other applications with similar phase shifting requirements. In addition, the design is resource efficient and is suitable for cost-effective digital implementation with a large number of channels.

show abstract

VMM1 - An ASIC for micropattern detectors

Cited by 30 publications

References 11 publications

Prototype board development for the validation of the VMM ASICs for the new small wheel ATLAS upgrade project

Prototype board development for the validation of the VMM ASICs for the new small wheel ATLAS upgrade project

Level-1 data driver card of the ATLAS new small wheel upgrade compatible with the phase II 1 MHz readout scheme

A programmable time alignment scheme for detector signals from the upgraded muon spectrometer at the ATLAS experiment

Contact Info

Product

Resources

About