VLSI technology trends

Abstract

The trends in VLSI / ULSI technologies are outlined in this paper, with a focus on ASIC (Application Specific IC) and Gate Array.The impact of the presently evolving BICMOS technology on VLSI is discussed, especially in light of CMOS at low temperatures.Packaging technology will play a major role on future VLSI chip technology and design. It will be one of the key technical items on product competitiveness. Thin film packages -preferably on silicon-for economic reasons very probably will break the trend to ever increasing chip sizes. Brickwall packaged VLSI chips connected via extremely wide buses to memory chips on the same carrier, result in high processor performance at lowest cost. Cooled down t o liquid nitrogen temperatures (LNT) by means of a cold plate, those (multi-) processors on a single substrate will attack the performance range of bipolar systems at a fraction of their cost. I . INTRODUCTIONWill CMOS maintain its leadership position in VLSI technology, or will BICMOS -or even GaAS or Bipolartechnologies be the choice of the future leading edge VLSI / ULSI components?This question is rather easily to be answered with regard to GaAs. Despite obvious progress in materials, process and circuit development / I / , GaAs is still suffering from its long infancy. Breakthroughs in high uniformity material and improved surface processing allows to produce chips up to a very few thousands of gates. Despite advantages in logic circuit speed over conventional state of the art CMOS,the need for additional time consuming chip crossingsbecause of the >lox lower chip circuit count-,reduces the performance advantage on a product level. Finally, the still very high production cost will prevent GaAs to be the winner in the VLSI arena within the next 5 years.The future potential of Bipolar and BICMOS versus CMOS has to be discussed considering and including the appropriate packaging technologies. So far packaging has been a more or less minor support function for VLSI chips, developed from bipolar packages, designed to support for high DC currents. In the future, the first level packaging (module) for CMOS VLSI chips -asking for extremely high AC currents in the range of IOA/nshas to be viewed an integral part of the VLSI chips, with significant impact on VLSI chip development and chip design concepts. Performance and even more cost of a VLSI product will be influenced severely by the right and optimized packaging technology. This is enforced when a LNT (Liquid Nitrogen Temperature) operation of CMOS is considered, with some unique requirements on packaging technology and a 2x performance improvement capability over roomtemperature operation.The die size trend of VLSI chips is still increasing according to Fig.6. However, for economical reasons and electro physical reasons / 2 / , this trend is unlikely to be continued. As outlined in section 6, the development of CMOS VLSI optimized packaging technologies allow to keep the chip sizes close to constant, without impact on processor performance, and even better packaged d...

Physical limits of silicon transistors and circuits

“…The statistical mechanics view yields an exponentially declining number of wires analogous to a Boltzmann distribution as length increases and does not fit the cases examined by Donath (1981) and Davis et al (2001) well. However, examples of exponential distributions can be found (Gardner 1987, Koetzle 1987, Nishi 1988. Models based on simple rules, though useful guides, do not capture the full limits on wiring.…”