VLSI Reed Solomon Decoder Design

Maki, G.K.; Owsley, Patrick A.; Cameron, K.; Venbrux, Jack

doi:10.1109/milcom.1986.4805860

Cited by 8 publications

(3 citation statements)

References 2 publications

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“…The introduced cellular structure is not optimized for any specific set of values of code parameters. Therefore, it is not easy and fair to compare the complexity and throughput of this structure with those of decoders or structures designed for fixed and specific coding parameters [4], [5], [6], [7], [8]. In this section, complexity and throughput of the introduced cellular structure are examined for various values of m.…”

Section: Complexity and Throughputmentioning

confidence: 99%

“…These structures can decode a large range of RS codes but they are not cellular and are very complex to be designed. Other structures have also been presented [4], [5], [6], [7], [8] based on algebraic or transform decoding algorithms which are suitable for RS decoders with specific error correction capability. These structures can be used to design RS decoders on a single VLSI chip with low complexity and high throughput.…”

Section: Introductionmentioning

confidence: 99%

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A cellular structure for a versatile Reed-Solomon decoder

Shayan¹,

Le‐Ngoc

1997

IEEE Trans. Comput.

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A new cellular structure for a versatile Reed-Solomon (RS) decoder is introduced based on time domain decoding algorithm. The time domain decoding algorithm is restructured to be suitable for introducing the cellular structure. The main advantages of this structure are its versatility and very simple cellular structure. By versatile decoder we mean a decoder that can be programmed to decode any (n, k) RS code defined in Galois field 2 m with a fixed block length n and a fixed symbol size m. This decoder can correct both errors and erasures for any message length k. The introduced decoder is cellular and has a very simple structure and hence it is suitable for VLSI designs. Index Terms-Cellular structure, comparison of RS decoding structures, time domain RS decoder, versatile RS decoder, VLSI.

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Section: Complexity and Throughputmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A cellular structure for a versatile Reed-Solomon decoder

Shayan¹,

Le‐Ngoc

1997

IEEE Trans. Comput.

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“…Work under NASA contract has resulted in a decoder chip set which consists of four custom VLSI devices that operate at rates up to 80 Mbps [2]. Within the European community, both Schlumberger Industries and Matra Espace have developed single chip coder/decoders that operate up to 25 Mbps [3,4].…”

Section: Introductionmentioning

confidence: 99%

A single-chip deinterleaving Reed-Solomon decoder for high performance CCSDS telemetry

Bennett

Grebowsky

Purdy³

et al.

[Proceedings] NTC-92: National Telesystems Conference

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Space telemetry protocols based upon recommendations by the Consultative Committee for Space Data Systems (CCSDS) are gaining wide acceptance within the international space telemetry community. These recommendations specify a very powerful interleaved Reed-Solomon code to protect its multi-layered, datadriven protocol format. As spacecraft telemetry data rates continue to increase, the computationally intensive nature of Reed-Solomon error correction requires a high-performance solution for space telemetry acquisition systems. This paper describes the development of a single-chip deinterleaving Reed-Solomon Error Correction decoder that demonstrates low-cost error correction for CCSDS-compatible data streams. This ReedSolomon Error Correction chip, designed to operate at rates up to 300 Megabits per second (Mbps), also incorporates additional onchip features such as cumulative quality accounting, real-time quality trailer generation, and fill frame removal.

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