VLSI implementations of image and video multimedia processing systems

Pirsch, P.; Stolberg, H.-J.

doi:10.1109/76.735383

Cited by 66 publications

(16 citation statements)

References 47 publications

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“…There have been significant improvements in processing multi-media data for transmission and display of information owing to continuous developments in the areas of signal processing, communication system, and VLSI technology [1]. The LCD (Liquid Crystal Display) must be one of the main driving forces for displaying the image and video signals.…”

Section: Introductionmentioning

confidence: 99%

High-capacity DC-DC converters for active matrix OLED display

Lee

Yoon

Kim

et al. 2010

2010 IEEE Asia Pacific Conference on Circuits and Systems

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Two DC-DC converters for bipolar outputs is implemented which are suitable for large-size AM-OLED (Active-Matrix Organic Light Emitting Diode) display. The positive output voltage is regulated by a buck DC-DC converter, and the negative one is regulated by a inverting buck-boost DC-DC converter. Both DC-DC converters operate in a current mode in order to enhance the transient responses. The improved discrete-mode detection circuit is proposed to achieve high-efficiency and accurate output voltages when converters operate in discontinuous-conduction mode. Compensation blocks such as artificial ramp and PI-compensator are incorporated for maintaining stability. The DC-DC converters are fabricated in a 0.35-um BCD technology. For typical operating conditions, maximum efficiencies of buck and inverting buck-boost converters are 92% and 83.1%, respectively.

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Section: Introductionmentioning

confidence: 99%

High-capacity DC-DC converters for active matrix OLED display

Lee

Yoon

Kim

et al. 2010

2010 IEEE Asia Pacific Conference on Circuits and Systems

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“…Since the operating frequency and voltage have practical and economical limits, execution parallelism has to be utilized. Surveys of the parallelization strategies for both dedicated, programmable and hybrid architectures are given in [2,3].…”

Section: Introductionmentioning

confidence: 99%

Scalable Architecture for SoC Video Encoders

Kangas

Hämäläinen

Kuusilinna

2006

J VLSI Sign Process Syst Sign Image Video Technol

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Evolving video coding standards demand functional flexibility for implementations, not only at design time but also after fabrication. This paper presents a System-on-Chip design approach with a feasible combination of performance, scalability, programmability, area efficiency, and design time effort for a video encoder. The encoder is based on a homogeneous master-slave processor architecture. Each slave encodes a part of the frame in the Single Program Multiple Data (SPMD) data parallel model. Both shared and distributed memory architectures are presented. Design effort is reduced by identical program codes, automated assembly of software and hardware modules independent of the number and type of processors, as well as our flexible on-chip communication network called Heterogeneous IP Block Interconnection (HIBI). A case study implementation with two to ten simple ARM7 processors, 32-bit HIBI bus and non-optimized processor-independent software gives the performance from 6 to 53 fps for QCIF. The whole encoder area ranges from 173 to 770 kgates excluding the memories. The relation scales reasonably well to systems with more powerful processors and optimized code. The optimization of the communication network shows that with more than six slaves even a serial HIBI connection with 100 MHz speed is feasible. HIBI and the parallelization approach allow exploration and optimization of the communication both at the application and architecture layers.

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“…Numerous architectures have been developed for image processing systems 10 . Efficient handling of the two-dimensional image data is a common issue among these designs.…”

Section: Introductionmentioning

confidence: 99%

Analysis of area-time efficiency for an integrated focal plane architecture

Robinson

Wills

2003

SPIE Proceedings

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Monolithic integration of photodetectors, analog-to-digital converters, digital processing, and data storage can improve the performance and efficiency of next-generation portable image products. Our approach combines these components into a single processing element, which is tiled to form a SIMD focal plane processor array with the capability to execute early image applications such as median filtering (noise removal), convolution (smoothing), and inside edge detection (segmentation). Digitizing and processing a pixel at the detection site presents new design challenges, including the allocation of silicon resources. This research investigates the area-time (A•T 2 ) efficiency by adjusting the number of Pixels-per-Processing Element (PPE). Area calculations are based upon hardware implementations of components scaled for 250nm or 120nm technology. The total execution time is calculated from the sequential execution of each application on a generic focal plane architectural simulator. For a Quad-CIF system resolution (176 x 144), results show that 1 PPE provides the optimal area-time efficiency (5.7 µs 2 • mm 2 for 250nm, 1.7 µs 2 • mm 2 for 120nm) but requires a large silicon chip (2072mm 2 for 250nm, 614mm 2 for 120nm). Increasing the PPE to 4 or 16 can reduce silicon area by 48% and 60% respectively (120nm technology) while maintaining performance within real-time constraints.

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VLSI implementations of image and video multimedia processing systems

Cited by 66 publications

References 47 publications

High-capacity DC-DC converters for active matrix OLED display

High-capacity DC-DC converters for active matrix OLED display

Scalable Architecture for SoC Video Encoders

Analysis of area-time efficiency for an integrated focal plane architecture

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