VLSI implementation of Tausworthe random number generator for parallel processing environment

Saarinen, Jukka; Tomberg, J.; Vehmanen, L.; Kaski, Kimmo

doi:10.1049/ip-e.1991.0019

Cited by 12 publications

(6 citation statements)

References 4 publications

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“…In these implementations, pseudorandom number generators or a random sequence generator are being used. These are algorithms that produce a sequence of numbers in a random like way by using two things: an initial condition and seed [21]. The initial condition will determine where the sequence will start.…”

Section: Motivation Of Research For This Thesismentioning

confidence: 99%

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Random Number Generator

2005

Dictionary of Statistics &Amp; Methodology

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Section: Motivation Of Research For This Thesismentioning

confidence: 99%

“…In [21], the authors have presented the implementation of Tausworthe random number generator optimized for parallel processing environments. They did a VLSI implementation in silicon and simulated using Monte-Carlo simulation.…”

Section: Digital Random Number Generatorsmentioning

confidence: 99%

Random Number Generator

2005

Dictionary of Statistics &Amp; Methodology

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“…However, the modulation dynamics for a ring topology is entirely different by nature of the feedback. Closing the loop implies (18) for any cell The complex eigenvalues in the -domain, satisfying are given by (19) and the eigenvectors, satisfying are correspondingly (20) The general solution in the time-domain is then given by (21) where the complex constants are expressed in terms of the initial conditions as…”

Section: B Dynamics Of Chain and Ring Topologiesmentioning

confidence: 99%

“…Most commonly used in parallel VLSI are arrays of random binary sources implemented with linear feedback shift registers (LFSR) [15], [16] or cellular automata (CA) [17], [18], which yield compact and scalable parallel VLSI architectures [20]- [22]. Analog random vectors with a near-gaussian amplitude profile can be obtained from the binary random vectors through low-pass filtering [19], [23].…”

Section: Introductionmentioning

confidence: 99%

Delta-sigma cellular automata for analog VLSI random vector generation

Cauwenberghs

1999

IEEE Trans. Circuits Syst. II

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Abstract-We present a class of analog cellular automata for parallel analog random vector generation, including theory on the randomness properties, scalable parallel very large scale integration (VLSI) architectures, and experimental results from an analog VLSI prototype with 64 channels. Linear congruential coupling between cells produces parallel channels of uniformly distributed random analog values, with statistics that are uncorrelated both across channels and over time.

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“…We use a parallel implementation of the Tausworthe random number generator to create a long uniformly distributed sequence [Tausworthe 1965;Saarinen et al 1991;Barel 1983]. Such a sequence can be converted to any other distribution by a table lookup and interpolation.…”

Section: Traffic Generator Modulesmentioning

confidence: 99%

A reconfigurable hardware approach to network simulation

Stiliadis

Varma

1997

ACM Trans. Model. Comput. Simul.

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Providing Quality-of-Service (QoS) guarantees in a broadband Asynchronous Transfer Mode (ATM) network places stringent demands on the network switches. Although analytical techniques may be used to bound the worst-case performance of traffic scheduling and congestion control algorithms, these are often inadequate for modeling the switch algorithms at the needed level of detail. Simulation is often the only alternative for evaluating the actual performance of the network. However, owing to the small size of the ATM cell and the high link-speeds, simulation of ATM switches and networks in a computationally demanding problem. To address this problem, we have developed a flexible hardware testbed for simulation of ATM-based networks. The testbed, called FAST (FPGA-based ATM simulation testbed), uses high-density field-programmable gate arrays (FPGAs) to allow implementation of the key algorithms in an ATM switch in hardware. The first version of the testbed (FAST-1) consists of a set of boards, each providing a total of 336,000 usable gates and 17 Mbytes of static RAM. Each board can be used to simulate an ATM switch, and multiple boards may be interconnected to simulate networks of ATM switches. Software tools have been developed for specifying the components of the switch model and algorithms, configuring the testbed for simulation, and monitoring the simulation process. This article provides an overview of the architecture of the FAST-1 board, describes its key components, and discusses some example simulation models of traffic scheduling algorithms using the board.

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VLSI implementation of Tausworthe random number generator for parallel processing environment

Cited by 12 publications

References 4 publications

Random Number Generator

Random Number Generator

Delta-sigma cellular automata for analog VLSI random vector generation

A reconfigurable hardware approach to network simulation

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