VLSI Implementation of Restricted Coulomb Energy Neural Network with Improved Learning Scheme

Cho, Jaechan; Jung, Yongchul; Lee, Seongjoo; Jung, Yunho

doi:10.3390/electronics8050563

Cited by 5 publications

(9 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In contrast, a restricted coulomb energy neural network (RCE-NN) generates neurons as needed during the learning process. This allows the network structure to adjust flexibly, making it well-suited for various sensor applications on edge devices [ 10 ]. In addition, the computation for learning and recognition in RCE-NNs involves simultaneously calculating the distance between the input feature vector and learned parameters and comparing the outputs of activated neurons.…”

Section: Introductionmentioning

confidence: 99%

“…In addition, the computation for learning and recognition in RCE-NNs involves simultaneously calculating the distance between the input feature vector and learned parameters and comparing the outputs of activated neurons. Given this low-complexity computational structure and parallelism, the RCE-NN was implemented as a hardware accelerator capable of real-time processing [ 10 , 11 , 12 ]. The authors of [ 10 ] proposed an improved RCE-NN learning algorithm that can achieve a high classification accuracy with fewer neurons than the basic RCE-NN algorithm.…”

Section: Introductionmentioning

confidence: 99%

“…Given this low-complexity computational structure and parallelism, the RCE-NN was implemented as a hardware accelerator capable of real-time processing [ 10 , 11 , 12 ]. The authors of [ 10 ] proposed an improved RCE-NN learning algorithm that can achieve a high classification accuracy with fewer neurons than the basic RCE-NN algorithm. They presented the results of a high-speed and low-power very-large-scale integrated circuit (VLSI) implementation.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Design of Network-on-Chip-Based Restricted Coulomb Energy Neural Network Accelerator on FPGA Device

Kang,

Lee,

Jung

2024

Sensors

Self Cite

View full text Add to dashboard Cite

Sensor applications in internet of things (IoT) systems, coupled with artificial intelligence (AI) technology, are becoming an increasingly significant part of modern life. For low-latency AI computation in IoT systems, there is a growing preference for edge-based computing over cloud-based alternatives. The restricted coulomb energy neural network (RCE-NN) is a machine learning algorithm well-suited for implementation on edge devices due to its simple learning and recognition scheme. In addition, because the RCE-NN generates neurons as needed, it is easy to adjust the network structure and learn additional data. Therefore, the RCE-NN can provide edge-based real-time processing for various sensor applications. However, previous RCE-NN accelerators have limited scalability when the number of neurons increases. In this paper, we propose a network-on-chip (NoC)-based RCE-NN accelerator and present the results of implementation on a field-programmable gate array (FPGA). NoC is an effective solution for managing massive interconnections. The proposed RCE-NN accelerator utilizes a hierarchical–star (H–star) topology, which efficiently handles a large number of neurons, along with routers specifically designed for the RCE-NN. These approaches result in only a slight decrease in the maximum operating frequency as the number of neurons increases. Consequently, the maximum operating frequency of the proposed RCE-NN accelerator with 512 neurons increased by 126.1% compared to a previous RCE-NN accelerator. This enhancement was verified with two datasets for gas and sign language recognition, achieving accelerations of up to 54.8% in learning time and up to 45.7% in recognition time. The NoC scheme of the proposed RCE-NN accelerator is an appropriate solution to ensure the scalability of the neural network while providing high-performance on-chip learning and recognition.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Design of Network-on-Chip-Based Restricted Coulomb Energy Neural Network Accelerator on FPGA Device

Kang,

Lee,

Jung

2024

Sensors

Self Cite

View full text Add to dashboard Cite

show abstract

“…On the contrary, restricted coulomb energy (RCE) neural networks employ a relatively simple training method [20] and can thus perform real-time learning [21]. An RCE neural network consists of neurons, and each neuron has a center point and a radius, which forms an activation region.…”

Section: Introductionmentioning

confidence: 99%

IMU Sensor-Based Hand Gesture Recognition for Human-Machine Interfaces

Kim

Cho

Lee

et al. 2019

Sensors

Self Cite

118

View full text Add to dashboard Cite

We propose an efficient hand gesture recognition (HGR) algorithm, which can cope with time-dependent data from an inertial measurement unit (IMU) sensor and support real-time learning for various human-machine interface (HMI) applications. Although the data extracted from IMU sensors are time-dependent, most existing HGR algorithms do not consider this characteristic, which results in the degradation of recognition performance. Because the dynamic time warping (DTW) technique considers the time-dependent characteristic of IMU sensor data, the recognition performance of DTW-based algorithms is better than that of others. However, the DTW technique requires a very complex learning algorithm, which makes it difficult to support real-time learning. To solve this issue, the proposed HGR algorithm is based on a restricted column energy (RCE) neural network, which has a very simple learning scheme in which neurons are activated when necessary. By replacing the metric calculation of the RCE neural network with DTW distance, the proposed algorithm exhibits superior recognition performance for time-dependent sensor data while supporting real-time learning. Our verification results on a field-programmable gate array (FPGA)-based test platform show that the proposed HGR algorithm can achieve a recognition accuracy of 98.6% and supports real-time learning and recognition at an operating frequency of 150 MHz.

show abstract

“…Our ears lies the most power dense information-processing unit that known to science as the brain. If computers are able to do the processing either as efficiently or as quickly as the brain, then Von-Newman architectures would become outmoded [1,2,19]. The outside of neural networks of an analog forward propagation network is an example of a software algorithm.…”

Section: Introductionmentioning

confidence: 99%

Use of Virtual Forward Propagation Network Model to Translate Analog Components

Ullah¹,

Brickner²,

Fouad³

2020

CSSP

View full text Add to dashboard Cite

Neural computing is an emerging research topic today due to its massive increase in demand and applications for machine learning. In this virtual simulation research work, using a free software, a program has been trained a neural network model and translate its functionality into the hardware. In the context of analog neural network, this research seeks to verify a shift sigmoid function that can approximate the transfer function of CMOS inverter. By showing this approximation accurately and reducing the number of components, it would help to implement the neural network based integrated chips. A conciliation is selected for the distance matric of the proposed function. This distance metric between the given CMOS transfer function and the shifted sigmoid function is minimized using the gradient descent. However, this approximate transfer function of CMOS inverter is chosen to verify in a three-layer perceptron networks. The network topology randomly generates weights to provide a diverse set of truth tables. We report two networks whose weights are chosen randomly using a back propagation algorithm due to volatile nature of the network topology and the activation function. The results of this research conclude that the transfer function of CMOS inverter is able to approximate the CMOS transfer function adequately for the purposes of these perceptron networks.

show abstract

VLSI Implementation of Restricted Coulomb Energy Neural Network with Improved Learning Scheme

Cited by 5 publications

References 18 publications

Design of Network-on-Chip-Based Restricted Coulomb Energy Neural Network Accelerator on FPGA Device

Design of Network-on-Chip-Based Restricted Coulomb Energy Neural Network Accelerator on FPGA Device

IMU Sensor-Based Hand Gesture Recognition for Human-Machine Interfaces

Use of Virtual Forward Propagation Network Model to Translate Analog Components

Contact Info

Product

Resources

About