IEEE Technology Students' Symposium 2011
DOI: 10.1109/techsym.2011.5783844
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VLSI implementation of MQ decoder in JPEG2000

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Cited by 5 publications
(3 citation statements)
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“…The real-time realization of several algorithms reduced the frame rate requirement. Kulkarni et al [37] proposed the high-speed and area-efficient architecture implemented on Virtex 2 FPGA. The high-frequency and the low hardware costs were achieved by using the Virtex 2 FPGA.…”
Section: Related Workmentioning
confidence: 99%
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“…The real-time realization of several algorithms reduced the frame rate requirement. Kulkarni et al [37] proposed the high-speed and area-efficient architecture implemented on Virtex 2 FPGA. The high-frequency and the low hardware costs were achieved by using the Virtex 2 FPGA.…”
Section: Related Workmentioning
confidence: 99%
“…Table 6 presents the comparative analysis of proposed PET with the existing novel MQ-decoder [11], flexible JPEG-2000 [38], VLSI-based JPEG2000 [37], FPGA-based binary arithmetic MQ-coder [21] for Virtex 2-XC2V6000-6 architecture.…”
Section: Device Utilizationmentioning
confidence: 99%
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