VLSI Implementation of Lattice Wave Digital Filters Using Fixed Point Arithmetic for Increased Maximum Sampling Frequency

Meenakshi, A.; Kr, Tarun

doi:10.4172/2324-9307.1000138

Cited by 2 publications

(3 citation statements)

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“…The implementation of a single notch filter using all-pass filter is shown in Figure 13(a). The comb filter of order L can be obtained by replacing z with z L in the transfer function of Equation (18), that is, where…”

Section: Design and Fpga Implementation Of Multiplierless Comb Filtermentioning

confidence: 99%

“…In past, LWDF structures were frequently used for realizing lowpass-highpass filter, bandpass-bandstop filter, and Hilbert transformers [14][15][16][17]. Their resulting structures were found to have minimum hardware, highly modular, and less sensitive, making them suitable for signal processors and VLSI implementation [18,19]. Thus, in order to incorporate the advantageous properties of LWDF with utilization of minimum multiplier, the design and structural realization of the comb filter is carried out using LWDF.…”

Section: Introductionmentioning

confidence: 99%

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Design and FPGA implementation of multiplierless comb filter

Barsainya

Agarwal

Rawat

2017

Circuit Theory & Apps

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Summary The main objective of this paper is to design and implement minimum multiplier, low latency structures of a comb filter. Multipliers are the most area and power consuming elements; therefore, it is desirable to realize a filter with minimum number of multipliers. In this paper, design of comb filters based on lattice wave digital filters (LWDF) structure is proposed to minimize the number of multipliers. The fundamental processing unit employed in LWDF requires only one multiplier. These lattice wave digital comb filters (LWDCFs) are realized using Richards' and transformed first‐order and second‐order all‐pass sections. The resulting structural realizations of LWDCFs exhibit properties such as low coefficient sensitivity, high dynamic range, high overflow level, and low round‐off noise. Multiplier coefficients of the proposed structures are implemented with canonic signed digit code (CSDC) technique using shift and add operations leading to multiplierless implementation. This contributes in reduction of number of addition levels which reduces the latency of the critical loop. A field programmable gate array (FPGA) platform is used for evaluation and testing of the proposed LWDCFs to acquire advantages of the parallelism, low cost, and low power consumption. The implementation of the proposed LWDCFs is accomplished on Xilinx Spartan‐6 and Virtex‐6 FPGA devices. By means of examples, it is shown that the implementations of the proposed LWDCFs attain high maximum sampling frequency, reduced hardware, and low power dissipation compared with the existing comb filter structures. Copyright © 2017 John Wiley & Sons, Ltd.

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Section: Design and Fpga Implementation Of Multiplierless Comb Filtermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design and FPGA implementation of multiplierless comb filter

Barsainya

Agarwal

Rawat

2017

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…Anderson et al have compared two port and three port series adaptor realizations of second-order allpass section but VLSI implementation is not done [7]. In [8], we have proposed the VLSI implementation of lattice WDF using three port series adaptor allpass structure which provides improved maximum sampling frequency compared to Richards' allpass structure based WDFs.…”

Section: Introductionmentioning

confidence: 99%