2006
DOI: 10.1007/s00500-006-0138-7
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VLSI implementation of greedy-based distributed routing schemes for ad hoc networks

Abstract: We describe a VLSI implementation based on a FPGA of a new greedy algorithm for approximating minimum set covering in ad hoc wireless network applications. The implementation makes the algorithm suitable for embedded and real-time architectures. The algorithm, while not randomized, is based on a probability distribution that leads the greedy choice. The algorithm has been specifically tailored to run on platforms with minimal computational hardware.

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Cited by 5 publications
(7 citation statements)
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“…Here we formalize such a cirumstance by representing G as a subset of 0, 1 2 , 1 n , where 1 2 represents the uncertain values.…”
Section: Adding Uncertaintymentioning
confidence: 99%
See 3 more Smart Citations
“…Here we formalize such a cirumstance by representing G as a subset of 0, 1 2 , 1 n , where 1 2 represents the uncertain values.…”
Section: Adding Uncertaintymentioning
confidence: 99%
“…In what follows, by an instance we shall mean an element of 0, 1 2 , 1 n and, if it is in {0, 1} n it will be called certain.…”
Section: Adding Uncertaintymentioning
confidence: 99%
See 2 more Smart Citations
“…Recently, in order to deal with incomplete training data, a machine learning algorithm, BRAIN (Batch Relevance-based Artificial INtelligence) [ 30 ], for binary classification rules has been generalized (U-BRAIN) [ 31 ]. This algorithm was originally conceived for recognizing splice junctions in human DNA (see also [ 32 , 33 ]). Splice junctions are points on a DNA sequence at which "superfluous" DNA is removed during the process of protein synthesis in higher organisms [ 34 ].…”
Section: Introductionmentioning
confidence: 99%