VLSI implementation of fast fourier transformation for OFDM-based high-speed wireless applications

Abstract

In this paper, we introduce a fixed-point 16bit 6"point FFT ))rocessor architecture for OFDM-base� wireless applications. The processor is based on DIT radh-2 butterfly FFT algorithm. The canaonical signed digital is used to implemcnt constant complex multil)lications with CSA tree for lower power and cost. The simulation shows the module can reach low cost\power and high speed for OFDM-based high-speed wireless applications.