VLSI implementation of discrete wavelet transform

Abstract

This paper presents a VLSI implementation of Discrete Wavelet Transform (DWT). The architecture is systolic in nature and performs both h i g h -p a s s and l o w -p a s s coefficient calculations with only one set of multipliers, in contrast to the approaches presented in the literature [ l ] , [2], [3]. The architecture is simple, modular, and cascadable, and has been implemented in VLSI.Experimental results show that real-time coefficient calculation on a 512 X 512 monochrome video input can he achieved with 1.2 pm technology.

A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000

“…Numerous architectures have been proposed for computing the 1D-DWT [5][6][7]11,12]. The 1D-DWT architectures can, in principle, be extended to architectures for computing the separable 2D-DWT.…”

Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems

“…In the literature, there have been many proposals devoted to the hardware architecture of DWT [5][6][7][8][9][10]. Most of the proposals based on fixed wavelet filter and fixed wavelet decomposition structure.…”

Systolic Architecture for Transposition-Free VLSI Implementation of Separable 2-D DWT

“…In the first stage, 1-D DWT is performed for each of the N columns of the input image to obtain an intermediate matrix. suggested for efficient systolic implementation of 1-D DWT; but they are not suitable for implementation of 2-D DWT for real-time applications due to their large initial delay [4]- [8]. To overcome the difficulties in implementation of separable devices, Pan et al [9]- [10] have suggested two architectures where transposition operation is taken care of by orthogonal processing of the rows and the columns.…”

“…Since, the 2-D DWT requires a large volume of computation; several architectural solutions are suggested in the last decade for its efficient implementation in dedicated VLSI. Among the existing VLSI systems, systolic structures form the most popular class, and keeping that in view, systolic architectures have been proposed for efficient VLSI implementation of the 2-D DWT [4], [8]- [10]. 2-D DWT can be implemented either by indirect (separable) approach or by direct (non-separable) approach.…”