VLSI implementation of a CORDIC SVD processor

Cavallaro, Joseph R.; Keleher, M.P.; Price, R. H.; Thomas, G.S.

doi:10.1109/ugim.1989.37346

Cited by 8 publications

(2 citation statements)

References 7 publications

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“…CORDIC architectures used in circular mode provide a flexible support for these functions and are typically proposed for the SVD implementation for real matrices, e.g. [11]. Figure 4 illustrates a possible architecture for the diagonal processors.…”

Section: B Architecture Candidates Of the Processorsmentioning

confidence: 99%

A reconfigurable pulsed UWB receiver sampling below Nyquist rate

Vanderperren

Leus

Dehaene

2008

2008 IEEE International Conference on Ultra-Wideband

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Section: B Architecture Candidates Of the Processorsmentioning

confidence: 99%

A reconfigurable pulsed UWB receiver sampling below Nyquist rate

Vanderperren

Leus

Dehaene

2008

2008 IEEE International Conference on Ultra-Wideband

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“…The CORDIC algorithm is present in digital modulation [4] or the robotics field [5], and can be used to compute the discrete cosine transform [6], the Hartley transform [7], or the singular value decomposition [8]. Moreover, the CORDIC algorithm is also used in space applications where sin(ωt) and cos(ωt) signals need to be digitally generated.…”

Section: Introductionmentioning

confidence: 99%

Radiation Hardened Digital Direct Synthesizer With CORDIC for Spaceborne Applications

et al. 2020

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The Coordinate Rotation Digital Computer algorithm (CORDIC) is a simple mechanism to compute a set of elementary functions, such as trigonometric functions, using fixed-point devices. It is widely adopted, also in applications running in harsh environments such as space, where radiation is a cause of errors in nanoelectronic devices. A single event upset in a configuration bit of a Field Programmable Gate Array (FPGA) can completely change the behavior of the implemented circuit, so it is important to detect and reconfigure the FPGA when this happens. Dual modular redundancy is the typical method to detect errors in electronic circuits, but it has an important overhead in area and power consumption and it does not provide any additional functionality apart from the activation of the FPGA reconfiguration trigger in presence of error. This paper presents two ad-hoc techniques to protect the Digital Direct Synthesizer with CORDIC when it is implemented into an FPGA, with limited overhead in terms of area and power consumption when compared with the traditional solution. The first solution slightly increases the percentage of undetected errors, about 11%, reducing to almost half the area overhead of the circuit. The second solution introduces a trade-off between the percentage of error detection and the precision of the trigonometric output of the CORDIC by means of a polymorphic structure with lower area resources than the existing solutions. This last proposal allows the system to increase the precision of the digital synthesis signal under absence of errors or to activate the error protection in scenarios with external disturbances such as radiation.

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Parallel VLSI architectures for real-time kinematics of redundant robots

Walker

Cavallaro

1994

J Intell Robot Syst

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VLSI implementation of a CORDIC SVD processor

Cited by 8 publications

References 7 publications

A reconfigurable pulsed UWB receiver sampling below Nyquist rate

A reconfigurable pulsed UWB receiver sampling below Nyquist rate

Radiation Hardened Digital Direct Synthesizer With CORDIC for Spaceborne Applications

Parallel VLSI architectures for real-time kinematics of redundant robots

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