VLSI implementation of 350 MHz 0.35 [micro sign]m 8 bit merged squarer

Efficient unsigned squarer design techniques

“…Table II compare the area, propagation delay and power consumption of various squarers, where "full" and "fixed" mean the full precision squarers and fixed-width squarers, respectively. Compared with the method in [2], the proposed method reduces the area, propagation delay and power consumption up to 18%, 10%, and 10%, respectively. Since the proposed squarers require a shorter CLA, there are small gains in delay for even W .…”

“…1 (b). To further reduce the depth of PPM, partial product bit rearrangement approach in [2] employs the following identity…”

“…The folding technique described in [1] uses the symmetry of the partial product matrix (PPM) of squarer to archive 50% reduction of the number of partial products compared with a standard multiplier. The partial products rearrangement technique in [2,3] is used to reduce the total number of partial product bits and the depth of PPM.…”

A Low Power High Performance Radix-4 Approximate Squaring Circuit

“…Approximate squaring circuits have numerous applications as mentioned in [12][13][14][15]20] such as cryptography, computation of Euclidean distance among pixels for a graphics processor or in rectangular to polar conversions in several signal processing circuits where full precision results are not required. As indicated in [14,25], customized squaring modules do have important applications in digital signal processing.…”

“…This property has been investigated to provide optimizations in multiplier design at the bit level [18,19]. The design focusing on a squaring circuit employing this symmetry was proposed in [21], and numerous studies optimizing binary squaring circuits appear in [12][13][14][15]20]. These designs primarily optimize by using hardwired bit product arrangements to reduce array sizes for efficient accumulation, mostly focusing on low precision.…”