VLSI design of power efficient Carry Skip Adder using TSG &amp;amp; Fredkin reversible gate

Chiwande, Sujata S.; Dakhole, Pravin

doi:10.1109/icdcsyst.2012.6188788

Cited by 7 publications

(1 citation statement)

References 2 publications

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“…Yu pang design revealed better reduction in energy dissipation due to use of reversible logic. A 4 bit CSK adder was designed using 4*4 reversible TSG & Fredkin gate by Chiwande and Dakhole [8]. The proposed adder in [8] demonstrated better reduction in power dissipation compared to existing four bit CSKAs.…”

Section: Introduction and Related Workmentioning

confidence: 99%

FPGA Implementation of High Speed Hardware Efficient Carry Select Adder

Saravanakumar

Vijeyakumar

Sakthisudhan

2018

IJRES

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This paper presents a novel architecture for high speed and hardware efficient carry select addition. We modify the two operand ripple carry addition followed in conventional Carry SeLect Adder(CSLA) with a simple and efficient gate level circuit to reduce area and delay significantly. For this, we use an increment 1 block for generating the sum outputs with carry input 1 instead of second pair ripple carry adder as in conventional CSLA. The novelty of the proposed approach is that it reduces area, and the delay due to carry propagation in second pair of adder cells. The proposed CSLA adder has been designed using structural VHDL code and synthesized using Altera Quartus II. Experimental results show that the proposed design outperform the previous approaches in terms of delay and area reduction.

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Section: Introduction and Related Workmentioning

confidence: 99%