VLSI design of 64bit × 64bit high performance multiplier with redundant binary encoding

Design and Analysis of Multipliers using Radix-8 Booth Encoding Technique for Low Power and Area Consumption

“…So, the conventional multipliers with high speed are not competent of on the condition that the high speed computational needs at low power requirements. [4]The Consequently implementing multipliers with high performance is one of the leading objectives for designers of system to enhance the entire performance of the systems [2]. So here in the beginning step, Modified Booth Encoding (MBE) is used strikingly to optimize the partial product by half [10].…”

“…Wallace trees which are some of the Partial product reduction schemes are used for partial product rows summation in the next step. In the step three, the final multiplication product is obtained by the two rows from partial product [5] summing tree which are added by means of fast carry-look ahead or carry save adder or carry select adders can be used [2]. A number of proceedings were put forward in the recent years to with the above three steps to achieve an efficient multiplier.…”

“…A number of proceedings were put forward in the recent years to with the above three steps to achieve an efficient multiplier. [2] By the module of modified booth encoding the partial product terms are reduced to half and thus credit the design of multiplier by decreasing the size and improving the speed of the summing tree [3]. Hence, the multipliers with high speed, low power and area [8] [9] in VLSI design has always been and is still a research subject.…”

“…One of the signed digit representations, for fast parallel arithmetic, redundant binary (RB) [1] representation is used. The specifications high modularity and addition without carry, made the usage of the representation in redundant binary in the design of high-speed multipliers [2]. The redundant binary number representation is engaged to perform signed digit arithmetic due to the fact that a redundant number can be represented in various forms.…”

“…Using redundant binary addition trees multipliers can be designed fast which posses advantageous features. Redundant Binary multipliers give reassuring output for high performance multiplication but increasing [2]. The performance of any of the VLSI circuit can be lowered by the delay of any gate used.…”